Enhanced Configuration (EPC) Devices Datasheet

ID 683253
Date 5/04/2016
Public
Give Feedback

1.3.1.1. Configuration Signals

Table 4.  Configuration Signals Connections Between EPC device and Altera FPGAs.
EPC Device Pin Altera FPGA Pin Description
DATA[] DATA[] Configuration data transmitted from the EPC device to the FPGA, which is latched on the rising edge of DCLK.
DCLK DCLK EPC device generated clock used by the FPGA to latch configuration data provided on the DATA[] pins.
nINIT_CONF nCONFIG Open-drain output from the EPC device that is used to start FPGA reconfiguration using the initiate configuration (INIT_CONF) JTAG instruction. This connection is not needed if the INIT_CONF JTAG instruction is not needed. If nINIT_CONF is not connected to nCONFIG, nCONFIG must be tied to VCC either directly or through a pull-up resistor.
OE nSTATUS Open-drain bidirectional configuration status signal, which is driven low by either the EPC device or FPGA during POR and to signal an error during configuration. Low pulse on OE resets the EPC device controller.
nCS CONF_DONE Configuration done output signal driven by the FPGA.