Enhanced Configuration (EPC) Devices Datasheet

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ID 683253
Date 5/04/2016
Public
Document Table of Contents
Document Table of Contents x
1. Enhanced Configuration (EPC) Devices Datasheet
1. Enhanced Configuration (EPC) Devices Datasheet x
1.1. Supported Devices 1.2. Features 1.3. Functional Description 1.4. Pin Description 1.5. Power-On Reset 1.6. Power Sequencing 1.7. Programming and Configuration File Support 1.8. IEEE Std. 1149.1 (JTAG) Boundary-Scan 1.9. Timing Information 1.10. Operating Conditions 1.11. Package 1.12. Document Revision History
1.3. Functional Description x
1.3.1. FPGA Configuration 1.3.2. External Flash Interface 1.3.3. Intel Flash-Based EPC Device Protection 1.3.4. Dynamic Configuration (Page Mode) 1.3.5. Real-Time Decompression 1.3.6. Programmable Configuration Clock 1.3.7. Flash In-System Programming (ISP)
1.3.1. FPGA Configuration x
1.3.1.1. Configuration Signals 1.3.1.2. Fast Passive Parallel Configuration 1.3.1.3. Passive Serial Configuration 1.3.1.4. Concurrent Configuration
1.3.7. Flash In-System Programming (ISP) x
1.3.7.1. JTAG-based Programming 1.3.7.2. Programming using External Flash Interface
1.11. Package x
1.11.1. Package Layout Recommendation
1. Enhanced Configuration (EPC) Devices Datasheet

1.3.3. Intel Flash-Based EPC Device Protection

In the absence of the lock bit protection feature in the EPC4, EPC8, and EPC16 devices with Intel flash, Altera recommends four methods to protect the Intel Flash content in EPC4, EPC8, and EPC16 devices. Any method alone is sufficient to protect the flash. The methods are listed here in the order of descending protection level:

  1. Using an RP# of less than 0.3 V on power-up and power-down for a minimum of 100 ns to a maximum 25 ms disables all control pins, making it impossible for a write to occur.
  2. Using VPP < VPPLK, where the maximum value of VPPLK is 1 V, disables writes. VPP < VPPLK means programming or writes cannot occur. VPP is a programming supply voltage input pin on the Intel flash. VPP is equivalent to the VCCW pin on EPC devices.
  3. Using a high CE# disables the chip. The requirement for a write is a low CE# and low WE#. A high CE# by itself prevents writes from occurring.
  4. Using a high WE# prevent writes because a write only occurs when the WE# is low.

Performing all four methods simultaneously is the safest protection for the flash content.

The following lists the ideal power-up sequence:

  1. Power up VCC.
  2. Maintain VPP < VPPLK until VCC is fully powered up.
  3. Power up VPP .
  4. Drive RP# low during the entire power-up process. RP# must be released high within 25 ms after VPP is powered up.
Note: CE# and WE# must be high for the entire power-up sequence.

The following lists the ideal power-down sequence:

  1. Drive RP# low for 100 ns before power-down.
  2. Power down VPP < VPPLK.
  3. Power down VCC.
  4. Drive RP# low during the entire power-down process.
Note: CE# and WE# must be high for the entire power-down sequence

The RP# pin is not internally connected to the controller. Therefore, an external loop-back connection between C-RP# and F-RP# must be made on the board even when you are not using the external device to the RP# pin with the loop-back connection. Always tri-state RP# when the flash is not in use.

If an external power up monitoring circuit is connected to the RP# pin with the loop-back connection, use the following guidelines to avoid contention on the RP# line:

  • The power-up sequence on the 3.3-V supply should complete within 50 ms of power up. The 3.3-V VCC should reach the minimum VCC before 50 ms and RP# should then be released.
  • RP# should be driven low by the power-up monitoring circuit during power up. After power up, RP# should be tri-stated externally by the power-up monitoring circuit.

If the preceding guidelines cannot be completed within 50 ms, then the OE pin must be driven low externally until RP# is ready to be released.

Level Two Title