Enhanced Configuration (EPC) Devices Datasheet

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ID 683253
Date 5/04/2016
Public
Document Table of Contents
Document Table of Contents x
1. Enhanced Configuration (EPC) Devices Datasheet
1. Enhanced Configuration (EPC) Devices Datasheet x
1.1. Supported Devices 1.2. Features 1.3. Functional Description 1.4. Pin Description 1.5. Power-On Reset 1.6. Power Sequencing 1.7. Programming and Configuration File Support 1.8. IEEE Std. 1149.1 (JTAG) Boundary-Scan 1.9. Timing Information 1.10. Operating Conditions 1.11. Package 1.12. Document Revision History
1.3. Functional Description x
1.3.1. FPGA Configuration 1.3.2. External Flash Interface 1.3.3. Intel Flash-Based EPC Device Protection 1.3.4. Dynamic Configuration (Page Mode) 1.3.5. Real-Time Decompression 1.3.6. Programmable Configuration Clock 1.3.7. Flash In-System Programming (ISP)
1.3.1. FPGA Configuration x
1.3.1.1. Configuration Signals 1.3.1.2. Fast Passive Parallel Configuration 1.3.1.3. Passive Serial Configuration 1.3.1.4. Concurrent Configuration
1.3.7. Flash In-System Programming (ISP) x
1.3.7.1. JTAG-based Programming 1.3.7.2. Programming using External Flash Interface
1.11. Package x
1.11.1. Package Layout Recommendation
1. Enhanced Configuration (EPC) Devices Datasheet

1.8. IEEE Std. 1149.1 (JTAG) Boundary-Scan

The EPC device provides JTAG BST circuitry that complies with the IEEE Std. 1149.1-1990 specification. JTAG BST can be performed before or after configuration, but not during configuration.

Figure 6. JTAG Timing Waveforms
Table 12.  JTAG Timing Parameters and Values
Symbol Parameter Min Max Unit
tJCP TCK clock period 100 — ns
tJCH TCK clock high time 50 — ns
tJCL TCK clock low time 50 — ns
tJPSU JTAG port setup time 20 — ns
tJPH JTAG port hold time 45 — ns
tJPCO JTAG port clock output — 25 ns
tJPZX JTAG port high impedance to valid output — 25 ns
tJPXZ JTAG port valid output to high impedance — 25 ns
tJSSU Capture register setup time 20 — ns
tJSH Capture register hold time 45 — ns
tJSCO Update register clock to output — 25 ns
tJSZX Update register high-impedance to valid output — 25 ns
tJSXZ Update register valid output to high impedance — 25 ns
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