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1.1. Supported Devices
1.2. Features
1.3. Functional Description
1.4. Pin Description
1.5. Power-On Reset
1.6. Power Sequencing
1.7. Programming and Configuration File Support
1.8. IEEE Std. 1149.1 (JTAG) Boundary-Scan
1.9. Timing Information
1.10. Operating Conditions
1.11. Package
1.12. Document Revision History
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1.3.1.4. Concurrent Configuration
EPC devices support concurrent configuration of multiple FPGAs (or FPGA chains) in PS mode. Concurrent configuration is when the EPC device simultaneously outputs n bits of configuration data on the DATA[n-1..0] pins (n = 1, 2, 4, or 8), and each DATA[] line serially configures a different FPGA chain. The number of concurrent serial chains is user-defined using the Quartus II software and can be any number from 1 to 8. For example, for three concurrent chains, you can select the 4-bit PS mode and connect the least significant DATA bits to the FPGAs or FPGA chains. Leave the most significant DATA bit (DATA[3]) unconnected. Similarly, for 5-, 6-, or 7-bit concurrent chains you can select the 8-bit PS mode.
Figure 3. Concurrent Configuration of Multiple FPGAs in PS Mode (n = 8)
| Mode Name | Mode (n =)3 | Used Outputs | Unused Outputs |
|---|---|---|---|
| PS mode | 1 | DATA0 | DATA[7..1] drive low |
| Multi-device PS | 2 | DATA[1..0] | DATA[7..2] drive low |
| Multi-device PS | 4 | DATA[3..0] | DATA[7..4] drive low |
| Multi-device PS | 8 | DATA[7..0] | — |
3 This is the number of valid DATA outputs for each configuration mode.