Enhanced Configuration (EPC) Devices Datasheet

ID 683253
Date 5/04/2016
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1.5. Power-On Reset

The POR circuit keeps the system in reset until power-supply voltage levels have stabilized. The POR time consists of the VCC ramp time and a user-programmable POR delay counter. When the supply is stable and the POR counter expires, the POR circuit releases the OE pin. The POR time can be further extended by an external device by driving the OE pin low.

Attention: Do not execute JTAG or ISP instructions until POR is complete.

The EPC device supports a programmable POR delay setting. You can set the POR delay to the default 100-ms setting or reduce the POR delay to 2 ms for systems that require fast power-up. The PORSEL input pin controls this POR delay—a logic-high level selects the 2-ms delay, while a logic-low level selects the 100-ms delay.

The EPC device enters reset under the following conditions:

  • The POR reset starts at initial power-up during VCC ramp-up or if VCC drops below the minimum operating condition anytime after VCC has stabilized
  • The FPGA initiates reconfiguration by driving nSTATUS low, which occurs if the FPGA detects a CRC error or if the FPGA’s nCONFIG input pin is asserted
  • The controller detects a configuration error and asserts OE to begin reconfiguration of the Altera FPGA (for example, when CONF_DONE stays low after all configuration data has been transmitted)