Enhanced Configuration (EPC) Devices Datasheet

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ID 683253
Date 5/04/2016
Public
Document Table of Contents
Document Table of Contents x
1. Enhanced Configuration (EPC) Devices Datasheet
1. Enhanced Configuration (EPC) Devices Datasheet x
1.1. Supported Devices 1.2. Features 1.3. Functional Description 1.4. Pin Description 1.5. Power-On Reset 1.6. Power Sequencing 1.7. Programming and Configuration File Support 1.8. IEEE Std. 1149.1 (JTAG) Boundary-Scan 1.9. Timing Information 1.10. Operating Conditions 1.11. Package 1.12. Document Revision History
1.3. Functional Description x
1.3.1. FPGA Configuration 1.3.2. External Flash Interface 1.3.3. Intel Flash-Based EPC Device Protection 1.3.4. Dynamic Configuration (Page Mode) 1.3.5. Real-Time Decompression 1.3.6. Programmable Configuration Clock 1.3.7. Flash In-System Programming (ISP)
1.3.1. FPGA Configuration x
1.3.1.1. Configuration Signals 1.3.1.2. Fast Passive Parallel Configuration 1.3.1.3. Passive Serial Configuration 1.3.1.4. Concurrent Configuration
1.3.7. Flash In-System Programming (ISP) x
1.3.7.1. JTAG-based Programming 1.3.7.2. Programming using External Flash Interface
1.11. Package x
1.11.1. Package Layout Recommendation
1. Enhanced Configuration (EPC) Devices Datasheet

1.5. Power-On Reset

The POR circuit keeps the system in reset until power-supply voltage levels have stabilized. The POR time consists of the VCC ramp time and a user-programmable POR delay counter. When the supply is stable and the POR counter expires, the POR circuit releases the OE pin. The POR time can be further extended by an external device by driving the OE pin low.

Attention: Do not execute JTAG or ISP instructions until POR is complete.

The EPC device supports a programmable POR delay setting. You can set the POR delay to the default 100-ms setting or reduce the POR delay to 2 ms for systems that require fast power-up. The PORSEL input pin controls this POR delay—a logic-high level selects the 2-ms delay, while a logic-low level selects the 100-ms delay.

The EPC device enters reset under the following conditions:

  • The POR reset starts at initial power-up during VCC ramp-up or if VCC drops below the minimum operating condition anytime after VCC has stabilized
  • The FPGA initiates reconfiguration by driving nSTATUS low, which occurs if the FPGA detects a CRC error or if the FPGA’s nCONFIG input pin is asserted
  • The controller detects a configuration error and asserts OE to begin reconfiguration of the Altera FPGA (for example, when CONF_DONE stays low after all configuration data has been transmitted)
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