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1.1. Supported Devices
1.2. Features
1.3. Functional Description
1.4. Pin Description
1.5. Power-On Reset
1.6. Power Sequencing
1.7. Programming and Configuration File Support
1.8. IEEE Std. 1149.1 (JTAG) Boundary-Scan
1.9. Timing Information
1.10. Operating Conditions
1.11. Package
1.12. Document Revision History
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1.3.7.1. JTAG-based Programming
The IEEE Std. 1149.1 JTAG Boundary Scan is implemented in EPC devices to facilitate the testing of its interconnection and functionality. EPC devices also support the ISP mode. The EPC device is compliant with the IEEE Std. 1532 draft 2.0 specification.
The JTAG unit of the configuration controller communicates directly with the flash memory. The controller processes the ISP instructions and performs the necessary flash operations. EPC devices support the maximum JTAG TCK frequency of 10 MHz.
During JTAG-based ISP, the external flash interface is not available. Before the JTAG interface programs the flash memory, an optional JTAG instruction (PENDCFG) can be used to assert the FPGA’s nCONFIG pin (using the nINIT_CONF pin). This will keep the FPGA in reset and terminate any internal flash access. This function prevents contention on the flash pins when both JTAG ISP and an external FPGA or processor try to access the flash simultaneously. The nINIT_CONF pin is released when the initiate configuration (nINIT_CONF) JTAG instruction is updated. As a result, the FPGA is configured with the new configuration data stored in flash.
You can add an initiate configuration (nINIT_CONF) JTAG instruction to your programming file in the Quartus II software by enabling the Initiate configuration after programming option in the Programmer options window (Options menu).