1.7. Programming and Configuration File Support
The Quartus II software provides programming support for the EPC device and automatically generates the .pof for the EPC4, EPC8, and EPC16 devices. In a multi-device project, the Quartus II software can combine the .sof for multiple ACEX 1K, APEX 20K, APEX II, Cyclone series, FLEX 10K, Mercury, and Stratix series FPGAs into one programming file for the EPC device.
EPC devices can be programmed in-system through the industry-standard 4-pin JTAG interface. The ISP feature in the EPC device provides ease in prototyping and updating FPGA functionality.
After programming an EPC device in-system, FPGA configuration can be initiated by including the EPC device’s JTAG INIT_CONF instruction.
The ISP circuitry in the EPC device is compliant with the IEEE Std. 1532 specification. The IEEE Std. 1532 is a standard that allows concurrent ISP between devices from multiple vendors.
|00 0101 0101
|Allows a snapshot of the state of the EPC device pins to be captured and examined during normal device operation and permits an initial data pattern output at the device pins.
|00 0000 0000
|Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing results at the input pins.
|11 1111 1111
|Places the 1-bit bypass register between the TDI and TDO pins, which allow the BST data to pass synchronously through a selected device to adjacent devices during normal device operation.
|00 0101 1001
|Selects the device IDCODE register and places it between TDI and TDO, allowing the device IDCODE to be serially shifted out to TDO. The device IDCODE for all EPC devices is 0100A0DDh
|00 0111 1001
|Selects the USERCODE register and places it between TDI and TDO, allowing the USERCODE to be serially shifted out the TDO. The 32-bit USERCODE is a programmable user-defined pattern.
|00 0110 0001
|This function initiates the FPGA reconfiguration process by pulsing the nINIT_CONF pin low, which is connected to the FPGA nCONFIG pin. After this instruction is updated, the nINIT_CONF pin is pulsed low when the JTAG state machine enters Run-Test/Idle state. The nINIT_CONF pin is then released and nCONFIG is pulled high by the resistor after the JTAG state machine goes out of Run-Test/Idle state. The FPGA configuration starts after nCONFIG goes high. As a result, the FPGA is configured with the new configuration data stored in flash using ISP. This function can be added to your programming file (.pof, .jam, and .jbc) in the Quartus II software by enabling the Initiate configuration after programming option in the Programmer options window (Options menu).
|00 0110 0101
|This optional function can be used to hold the nINIT_CONF pin low during JTAG-based ISP of the EPC device. This feature is useful when the external flash interface is controlled by an external FPGA or processor. This function prevents contention on the flash pins when both the controller and external device try to access the flash simultaneously. Before the EPC device’s controller can access the flash memory, the external FPGA/processor needs to tri-state its interface to flash.This can be ensured by resetting the FPGA using the nINIT_CONF, which drives the nCONFIG pin and keeps the external FPGA or processor in the “reset” state. The nINIT_CONF pin is released when the initiate configuration (INIT_CONF) JTAG instruction is issued.
EPC devices can also be programmed by third-party flash programmers or on-board processors using the external flash interface. Programming files (.pof) can be converted to a Hexadecimal (Intel-Format) File (.hexout) using the Quartus II Convert Programming Files utility, for use with the programmers or processors.
You can also program the EPC devices using the Quartus II software and the appropriate configuration device programming adapter.