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1.1. Supported Devices
1.2. Features
1.3. Functional Description
1.4. Pin Description
1.5. Power-On Reset
1.6. Power Sequencing
1.7. Programming and Configuration File Support
1.8. IEEE Std. 1149.1 (JTAG) Boundary-Scan
1.9. Timing Information
1.10. Operating Conditions
1.11. Package
1.12. Document Revision History
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1.3.4. Dynamic Configuration (Page Mode)
The dynamic configuration (or page mode) feature allows the EPC device to store up to eight different sets of designs for all the FPGAs in your system. You can then choose which page (set of configuration files) the EPC device should use for FPGA configuration.
Dynamic configuration or the page mode feature enables you to store a minimum of two pages—a factory default or fail-safe configuration and an application configuration. The fail-safe configuration page could be programmed during system production, while the application configuration page could support remote or local updates. These remote updates could add or enhance system features and performance. However, with remote update capabilities comes the risk of possible corruption of configuration data. In the event of such a corruption, the system could automatically switch to the fail-safe configuration and avoid system downtime.
The EPC device page mode feature works with the Stratix remote system configuration feature, to enable intelligent remote updates to your systems.
The three PGM[2..0] input pins control which page is used for configuration and these pins are sampled at the start of each configuration cycle when OE goes high. The page mode selection allows you to dynamically reconfigure the functionality of your FPGA by switching the PGM[2..0] pins and asserting nCONFIG. Page 0 is defined as the default page and the PGM[2] pin is the MSB.
Note: The PGM[2..0] input pins must not be left floating on your board. When you are not using this feature, connect the PGM[2..0] pins to GND to select the default page 000.
The EPC device pages are dynamically-sized regions in memory. The start address and length of each page is programmed into the option-bit space of the flash memory during initial programming. All subsequent configuration cycles sample the PGM[] pins and use the option-bit information to jump to the start of the corresponding configuration page. Each page must have configuration files for all FPGAs in your system that are connected to that EPC device.
For example, if your system requires three configuration pages and includes two FPGAs, each page will store two SRAM Object Files (.sof) for a total of six .sof in the configuration device.
Furthermore, all EPC device configuration schemes (PS, FPP, and concurrent PS) are supported with the page-mode feature. The number of pages, devices, or both, that can be configured using a single EPC device is only limited by the size of the flash memory.