Enhanced Configuration (EPC) Devices Datasheet

ID 683253
Date 5/04/2016
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1.3. Functional Description

The Altera EPC device is a single device with high speed and advanced configuration solution for high-density FPGAs. The core of an EPC device is divided into two major blocks—a configuration controller and a flash memory. The flash memory is used to store configuration data for systems made up of one or more than one Altera FPGAs. Unused portions of the flash memory can be used to store processor code or data that can be accessed using the external flash interface after the FPGA configuration is complete.

Table 2.  Supported EPC devices required to configure an ACEX 1K, APEX 1K, APEX 20K, APEX 20KC, APEX 20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 10KA, FLEX 10KE, Stratix, Stratix GX, Stratix II, Stratix II GX, or Mercury device.
Device Family Device Data Size (Bits)1 EPC Devices2
EPC4 EPC8 EPC16
Arria GX EP1AGX20C 9,640,672 1
EP1AGX35C
EP1AGX35D 9,640,672 1
EP1AGX50C
EP1AGX50D 16,951,824 1
EP1AGX60C
EP1AGX60D
EP1AGX60E 16,951,824 1
EP1AGX90E 25,699,104 1
Stratix EP1S10 3,534,640 1 1 1
EP1S20 5,904,832 1 1 1
EP1S25 7,894,144 1 1
EP1S30 10,379,368 1 1
EP1S40 12,389,632 1 1
EP1S60 17,543,968 1
EP1S80 23,834,032 1
Stratix GX EP1SGX10 3,534,640 1 1 1
EP1SGX25 7,894,144 1 1
EP1SGX40 12,389,632 1 1
Stratix II EP2S15 4,721,544 1 1 1
EP2S30 9,640,672 1 1
EP2S60 16,951,824 1
EP2S90 25,699,104
EP2S130 37,325,760
EP2S180 49,814,760
Stratix II GX EP2SGX30C 9,640,672 1
EP2SGX30D 9,640,672 1
EP2SGX60C 16,951,824 1
EP2SGX60D 16,951,824 1
EP2SGX60E 16,951,824 1
EP2SGX90E 25,699,104
EP2SGX90F 25,699,104
EP2SGX130G 37,325,760
Cyclone EP1C3 627,376 1 1 1
EP1C4 924,512 1 1 1
EP1C6 1,167,216 1 1 1
EP1C12 2,326,528 1 1 1
EP1C20 3,559,608 1 1 1
Cyclone II EP2C5 1,223,980 1 1 1
EP2C8 1,983,792 1 1 1
EP2C20 3,930,986 1 1 1
EP2C35 7,071,234 1 1
EP2C50 9,122,148 1 1
EP2C70 10,249,694 1 1
ACEX 1K EP1K10 159,160 1 1 1
EP1K30 473,720 1 1 1
EP1K50 784,184 1 1 1
EP1K100 1,335,720 1 1 1
APEX 20K EP20K100 993,360 1 1 1
EP20K200 1,950,800 1 1 1
EP20K400 3,880,720 1 1 1
APEX 20KC EP20K200C 1,968,016 1 1 1
EP20K400C 3,909,776 1 1 1
EP20K600C 5,673,936 1 1 1
EP20K1000C 8,960,016 1 1
APEX 20KE EP20K30E 354,832 1 1 1
EP20K60E 648,016 1 1 1
EP20K100E 1,008,016 1 1 1
EP20K160E 1,524,016 1 1 1
EP20K200E 1,968,016 1 1 1
EP20K300E 2,741,616 1 1 1
EP20K400E 3,909,776 1 1 1
EP20K600E 5,673,936 1 1 1
EP20K1000E 8,960,016 1 1
EP20K1500E 12,042,256 1 1
APEX II EP2A15 4,358,512 1 1 1
EP2A25 6,275,200 1 1 1
EP2A40 9,640,528 1 1
EP2A70 17,417,088 1
Table 3.  Supported Flash Memory for EPC Devices
Device Family Grade Package Flash Memory
Leaded Lead-Fee
EPC4 Commercial PQFP 100 Intel or Micron Intel or Micron
Industrial PQFP 100 Intel or Micron Intel
EPC8 Commercial/Industrial PQFP 100 Intel or Sharp Intel
EPC16 Commercial UBGA 884 Intel or Sharp Intel or Sharp
Industrial UBGA 884 Intel or Sharp Intel
Military UBGA 884 Intel Intel
Commercial/Industrial PQFP 100 Intel or Sharp Intel
Note: The external flash interface feature is supported in EPC4 and EPC16 devices. For more information about using this feature in the EPC8 device, contact Altera for support.

EPC devices have a 3.3-V core and I/O interface. The controller chip is a synchronous system that implements the various interfaces and features. The controller chip features three separate interfaces:

  • A configuration interface between the controller and the Altera FPGAs
  • A JTAG interface on the controller that enables ISP of the flash memory
  • An external flash interface that the controller shares with an external processor or FPGA implementing a Nios embedded processor—an interface available after ISP and configuration
Figure 1. EPC Device Block Diagram

The EPC device features multiple configuration schemes. In addition to supporting the traditional passive serial (PS) configuration scheme for a single device or a serial-device chain, the EPC device features concurrent configuration and parallel configuration. With the concurrent configuration scheme, up to eight PS device chains can be configured simultaneously. In the FPP configuration scheme, 8-bits of data are clocked into the FPGA during each cycle. These configuration schemes offer significantly reduced configuration times over traditional schemes.

Furthermore, the EPC device features a dynamic configuration or page mode feature. This feature allows you to dynamically reconfigure all the FPGAs in your system with new images stored in the configuration memory. Up to eight different system configurations or pages can be stored in the memory and selected using the PGM[2..0] pins. Your system can be dynamically reconfigured by selecting one of the eight pages and initiating a reconfiguration cycle.

This page mode feature combined with the external flash interface allows remote and local updates of system configuration data. The EPC devices are compatible with the remote system configuration feature of the Stratix device.

Other user programmable features include:

  • Real-time decompression of configuration data
  • Programmable configuration clock (DCLK)
  • Flash ISP
  • Programmable POR delay (PORSEL)
1 The Raw Binary File (.rbf) sizes are used to determine the data size for each device.
2 These values are calculated with the compression feature of the EPC device enabled.