Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 10/04/2021

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2.5.5. Correlating Constraints to the Timing Report

Understanding how timing constraints and violations appear in the timing analysis reports is critical to understanding the results. The following examples show how specific constraints impact the timing analysis reports. Most timing constraints only affect the clock launch and latch edges. Specifically, create_clock and create_generated_clock create clocks with default relationships. However, the set_multicycle_path exception modifies the default setup and hold relationships. The set_max_delay and set_min_delay constraints are low-level overrides that explicitly indicate the maximum and minimum delays for the launch and latch edges.

The figures show the results of running Report Timing on a particular path.

In the following example, the design includes a clock driving the source and destination registers with a period of 10 ns. This results in a setup relationship of 10 ns (launch edge = 0 ns, latch edge = 10ns) and hold relationship of 0 ns (launch edge = 0 ns, latch edge = 0 ns) from the command:
create_clock -name clocktwo -period 10.000 [get_ports {clk2}]
Figure 81. Setup Relationship 10ns, Hold Relationship 0ns
The set_multicycle_path constraint adds multicycles to relax the setup relationship, or open the window, making the setup relationship 20 ns while the hold relationship is still 0 ns:
set_multicycle_path -from clocktwo -to clocktwo -setup -end 2
set_multicycle_path -from clocktwo -to clocktwo -hold -end 1
Figure 82. Setup Relationship 20ns

The set_max_delay and set_min_delay constraints explicitly override the setup relationship. Note that the only thing changing for these different constraints are the launch edge time and latch edge times for setup and hold analysis. Every other line item comes from delays inside the FPGA and are static for a given fit. View these reports to analyze how your constraints affect the timing reports.

Figure 83. Using set_max_delay

For I/O, you must add set_input_delay and set_output_delay constraints. These constraints describe delays on signals from outside of the FPGA design that connect to the design's I/O ports. The values of these constraints are the delays of the external signals between an external register and a port on the design. The -clock argument to the set_input_delay and set_output_delay specifies the clock domain that the external signal belongs to, or rather, the clock domain of the external register connected to the I/O port. The -min and -max options specify the worst-case or best-case delay; not specifying either option causes the worst- and best-case delays to be equal. I/O delays display as iExt or oExt in the Type column. An example is an output port with a set_output_delay -max 1.0 and set_output_delay -min -0.5. Refer to "Creating Virtual Clocks" and "Creating I/O Constraints" for more information.

Figure 84. Using set_min_delay

A clock relationship, which is the difference between the launching and latching clock edge of a transfer, is determined by the clock waveform, multicycle constraints, and minimum and maximum delay constraints. The Timing Analyzer also adds the value of set_output_delay as an oExt value. For outputs this value is part of the Data Required Path, since this is the external part of the analysis. The setup report subtracts the -max value, making the setup relationship harder to meet, since the Data Arrival Path must be shorter than the Data Required Path. The Timing Analyzer also subtracts the -min value. This subtraction is why a negative number causes more restrictive hold timing. The Data Arrival Path must be longer than the Data Required Path.