Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 10/04/2021
Public

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1.1.1.3. Data and Clock Arrival Times

After the Timing Analyzer identifies the path type, the Timing Analyzer can report data and clock arrival times at register pins.

The Timing Analyzer calculates data arrival time by adding the launch edge time to the delay from the clock source to the clock pin of the source register, the micro clock-to-output delay ( µtCO) of the source register, and the delay from the source register’s data output (Q) to the destination register’s data input (D).

The Timing Analyzer calculates data required time by adding the latch edge time to the sum of all delays between the clock port and the clock pin of the destination register. It includes any clock port buffer delays and subtracts the micro setup time ( µtSU) (or adds the micro hold time) of the destination register. Where the µtSU is the intrinsic setup time of an internal register in the FPGA.

Figure 4. Data Arrival and Data Required Times

The basic calculations for data arrival and data required times including the launch and latch edges.

Figure 5. Data Arrival and Data Required Time Equations