1.1.1. Timing Path and Clock Analysis 1.1.2. Clock Setup Analysis 1.1.3. Clock Hold Analysis 1.1.4. Recovery and Removal Analysis 1.1.5. Multicycle Path Analysis 1.1.6. Metastability Analysis 1.1.7. Timing Pessimism 1.1.8. Clock-As-Data Analysis 1.1.9. Multicorner Timing Analysis 1.1.10. Time Borrowing
2.1. Timing Analysis Flow 2.2. Step 1: Specify Timing Analyzer Settings 2.3. Step 2: Specify Timing Constraints 2.4. Step 3: Run the Timing Analyzer 2.5. Step 4: Analyze Timing Reports 2.6. Applying Timing Constraints 2.7. Timing Analyzer Tcl Commands 2.8. Timing Analysis of Imported Compilation Results 2.9. Using the Intel® Quartus® Prime Timing Analyzer Document Revision History 2.10. Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer Archive
18.104.22.168. Report Fmax Summary 22.214.171.124. Report Timing 126.96.36.199. Report Data Delay 188.8.131.52. Report Clocks and Clock Networks 184.108.40.206. Report Clock Transfers 220.127.116.11. Report Logic Depth 18.104.22.168. Report Neighbor Paths 22.214.171.124. Report Register Spread 126.96.36.199. Report Route Net of Interest 188.8.131.52. Report Retiming Restrictions 184.108.40.206. Report Reset Statistics 220.127.116.11. Report Pipelining Information 18.104.22.168. Report Asynchronous CDC 22.214.171.124. Report CDC Viewer 126.96.36.199. Report Time Borrowing Data 188.8.131.52. Report Exceptions and Exceptions Reachability
2.6.1. Recommended Initial SDC Constraints 2.6.2. SDC File Precedence 2.6.3. Modifying Iterative Constraints 2.6.4. Using Entity-bound SDC Files 2.6.5. Creating Clocks and Clock Constraints 2.6.6. Creating I/O Constraints 2.6.7. Creating Delay and Skew Constraints 2.6.8. Creating Timing Exceptions 2.6.9. Using Fitter Overconstraints 2.6.10. Example Circuit and SDC File
184.108.40.206.1. Default Multicycle Analysis 220.127.116.11.2. End Multicycle Setup = 2 and End Multicycle Hold = 0 18.104.22.168.3. End Multicycle Setup = 2 and End Multicycle Hold = 1 22.214.171.124.4. Same Frequency Clocks with Destination Clock Offset 126.96.36.199.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency 188.8.131.52.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset 184.108.40.206.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency 220.127.116.11.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
1.1. Timing Analysis Basic Concepts
This user guide introduces the following concepts to describe timing analysis:
|The Timing Analyzer calculates the data and clock arrival time versus the required time at register pins.
|Device resource that contains look-up tables (LUT), registers, digital signal processing (DSP) blocks, memory blocks, or I/O elements. In Intel Stratix® series devices, the LUTs and registers are contained in logic elements (LE) modeled as cells.
|Named signal representing clock domains inside or outside of your design.
|More accurate timing analysis for complex paths that includes any phase shift associated with a PLL for the clock path, and considers any related phase shift for the data path.
|Clock hold time
|Minimum time interval that a signal must be stable on the input pin that feeds a data input or clock enable, after an active transition on the clock input.
|Clock launch and latch edge
|The launch edge is the clock edge that sends data out of a register or other sequential element, and acts as a source for the data transfer. The latch edge is the active clock edge that captures data at the data port of a register or other sequential element, acting as a destination for the data transfer.
|Clock pessimism refers to use of the maximum (rather than minimum) delay variation associated with common clock paths during static timing analysis.
|Clock setup time
|Minimum time interval between the assertion of a signal at a data input, and the assertion of a low-to-high transition on the clock input.
|Maximum or minimum delay constraint
|A constraint that specifies timing path analysis with a non-default setup or hold relationship.
|A collection of two or more interconnected components.
|Represents a wire carrying a signal that travels between different logical components in the design. Most basic timing netlist unit. Used to represent ports, pins, and registers.
|Inputs or outputs of cells.
|Top-level module inputs or outputs; for example, a device pin.
|Metastability problems can occur when a signal transfers between circuitry in unrelated or asynchronous clock domains. The Timing Analyzer analyzes the potential for metastability in your design and can calculate the MTBF for synchronization register chains.
|Timing analysis of slow and fast timing corners to verify your design under a variety of voltage, process, and temperature operating conditions.
|A data path that requires a non-default number of clock cycles for proper analysis.
|Recovery and removal time
|Recovery time is the minimum length of time for the deassertion of an asynchronous control signal relative to the next clock edge. Removal time is the minimum length of time the deassertion of an asynchronous control signal must be stable after the active clock edge.
|A Compiler-generated list of your design's synthesized nodes and connections. The Timing Analyzer requires this netlist to perform timing analysis.
|The wire connection (net) between any two sequential design nodes, such as the output of a register to the input of another register.