Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 10/04/2021
Public

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2.6.5.7. Constraining CDC Paths

You can apply false path constraints (set_false_path) to constrain clock domain crossing (CDC) paths.

The following examples show applying set_false_path for a design that contains a DCFIFO block to avoid timing failures in the synchronization registers. These examples are for constraining single-bit synchronizer CDC paths:

  • For paths crossing from the write into the read domain, apply a false path assignment between registers delayed_wrptr_g and rs_dgwp:
    set_false_path -from [get_registers {*dcfifo*delayed_wrptr_g[*]}] \
    -to [get_registers {*dcfifo*rs_dgwp*}]
  • For paths crossing from the read into the write domain, apply a false path assignment between registers rdptr_g and ws_dgrp:
    set_false_path -from [get_registers {*dcfifo*rdptr_g[*]}] \
    -to [get_registers {*dcfifo*ws_dgrp*}]