Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 10/04/2021
Public

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2.3. Step 2: Specify Timing Constraints

You must specify timing constraints that describe the clock frequency requirements, timing exceptions, and I/O timing requirements of your design for comparison against actual conditions during timing analysis. You define timing constraints in one or more Synopsys* Design Constraints (.sdc) files that you add to the project.

If you are unfamiliar with .sdc files, you can create an initial .sdc file in the Timing Analyzer GUI, or with provided .sdc file templates. If you are familiar with timing analysis, you can create an .sdc file in any text editor, and then add the file to the project.

  1. Use any combination of the following to enter the timing constraints for your design in an .sdc file:
    • Enter constraints in the Timing Analyzer GUI—click Tools > Timing Analyzer, click Update Timing Netlist in the Tasks pane, and then enter constraints from the Constraints menu. The GUI displays the corresponding SDC command that applies.
    • Create an .sdc file on your own. You can start by adding the Recommended Initial SDC Constraints, and then iteratively modify .sdc constraints and reanalyze the timing results. You must first create clock constraints before entering any constraints dependent on the clock.
    Figure 38. Create Clock Dialog Defines Clock Constraints
  2. Save the .sdc file. When entering constraints in the Timing Analyzer GUI, click Constraints > Write SDC File to save the constraints you enter in the GUI to an .sdc file.
  3. Add the .sdc file to your project, as Step 1: Specify Timing Analyzer Settings describes.