Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 10/04/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

2.6.1.3. Derive Clock Uncertainty (derive_clock_uncertainty)

The Derive Clock Uncertainty (derive_clock_uncertainty) constraint applies setup and hold clock uncertainty for clock-to-clock transfers in the design. This uncertainty represents characteristics like PLL jitter, clock tree jitter, and other factors of uncertainty.

You can enable the Add clock uncertainty assignment (-add) to add clock uncertainty values from any Set Clock Uncertainty (set_clock_uncertainty) constraint. You can Overwrite existing clock uncertainty assignments (-overwrite) any set_clock_uncertainty constraints.

create_clock -period 10.0 -name fpga_sys_clk [get_ports fpga_sys_clk] \
	derive_clock_uncertainty -add - overwrite

The Timing Analyzer generates an information message if you omit derive_clock_uncertainty from the .sdc file.