Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 10/04/2021
Public

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1.1.1.1. The Timing Netlist

The Timing Analyzer uses the timing netlist data to determine the data and clock arrival time versus required time for all timing paths in the design. You can generate the timing netlist in the Timing Analyzer any time after running the Fitter.

The following figures illustrate division of a simple design schematic into timing netlist delays.

Figure 1. Simple Design Schematic
Figure 2. Division of Elements into Timing Netlist Delays