Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 10/04/2021
Public

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2.6.8.1. Timing Exception Precedence

If the same clock or node names occur in multiple timing exceptions, the Timing Analyzer observes the following order of timing exception precedence:
  1. Set False Path (set_false_path) is the first priority. False paths and clock groups have identical priority, except when you use the -latency_insensitive or -no_synchronizer options with a false path exception. With either option, the false path has priority over a clock group.
  2. Set Clock Groups (set_clock_groups) is the second priority.
  3. Set Minimum Delay (set_min_delay) and Set Maximum Delay (set_max_delay) are the third priority.
  4. Set Multicycle Path (set_multicycle_path) is the fourth priority.
The false path timing exception has the highest precedence. Within each category, assignments to individual nodes have precedence over assignments to clocks. For exceptions of the same type:
  1. -from <node> is the first priority.
  2. -to <node> is the second priority.
  3. -thru <node> is the third priority.
  4. -from <clock> is the fourth priority.
  5. -to <clock> is the fifth priority.
An asterisk wildcard (*) for any of these options applies the same precedence as not specifying the option at all. For example, -from a -to * is treated identically to -from a with regards precedence.

Precedence example

  1. set_max_delay 1 -from x -to y
  2. set_max_delay 2 -from x
  3. set_max_delay 3 -to y

The first exception has higher priority than either of the other two, since the first exception specifies a -from (while #3 doesn't) and specifies a -to (while #2 doesn't). In the absence of the first exception, the second exception has higher priority than the third, since the second exception specifies a -from, which the third does not. Finally, the remaining order of precedence for additional exceptions is order-dependent, such that the assignments most recently created overwrite, or partially overwrite, earlier assignments.

The set_net_delay, set_max_skew, and set_data_delay constraints analyze independently of minimum or maximum delays, or multicycle path constraints.
  • The set_net_delay exception applies regardless of the existence of a set_false_path exception, or set_clock_groups exception, or other path-based constraint or exception. It is a net-based exception, and net-based and path-based exceptions are applied independently of each other.
  • The set_max_skew exception applies on paths cut by an asynchronous clock group, and regardless of any set_false_path exception. Exclusive clock groups override max skew exceptions, because paths between exclusive clocks are entirely inactive and should not be analyzed for timing or skew requirements. This precedence allows you to define more targeted constraints on asynchronous CDC bus transfers.
  • The set_data_delay exception specifies a maximum datapath delay exception for a given path. Exclusive clock groups override data delay exceptions, because paths between exclusive clocks are entirely inactive and should not be analyzed for timing or data delay requirements. Asynchronous clock groups do not override data delay exceptions. False path exceptions override data delay exceptions in the Intel Quartus Prime Pro software version 21.2 and earlier. Beginning in version 21.3, false path exceptions do not override data delay exceptions. This change in precedence allows you to write more targeted constraints on asynchronous CDC bus transfers.