Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 10/04/2021
Public

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2.6.6.2. Output Constraints (set_output_delay)

Output constraints specify all external delays from the device for all output ports in your design.
set_output_delay -clock { clock } -clock_fall -rise -max 2 foo

Use the Set Output Delay (set_output_delay) constraint to specify external output delay requirements. Specify the Clock name (-clock) to reference the virtual or actual clock. When specifying a clock, the clock defines the latching clock for the output port. The Timing Analyzer automatically determines the launching clock inside the device that launches the output data, because all clocks in the device are defined. The following figure is an example of an output delay referencing a virtual clock.

Figure 99. Output Delay Diagram
Figure 100. Output Delay Calculation

If your design includes partition boundary ports, you can use the -blackbox option with set_ouput_delay to assign output delays. The -blackbox option creates a new keeper timing node with the same name as the boundary port. This new node permits the propagation of timing paths through the original boundary port and acts as a set_output_delay constraint. The new keeper timing nodes display when you use the get_keepers command.

You can remove blackbox constraints with remove_output_delay -blackbox.