Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 10/04/2021
Public

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2.6.7.1. Advanced I/O Timing and Board Trace Model Delay

The Timing Analyzer can use advanced I/O timing and board trace model constraints to model I/O buffer delays in your design.

If you change any advanced I/O timing settings or board trace model assignments, recompile your design before you analyze timing, or use the -force_dat option to force delay annotation when you create a timing netlist.

Forcing Delay Annotation

create_timing_netlist -force_dat