Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 10/04/2021
Public

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2.1. Timing Analysis Flow

After creating your design and setting up a project, you define the required timing constraints for your design in a Synopsys* Design Constraints (.sdc) file. The Fitter then attempts to place logic to meet or exceed your constraints. The Timing Analyzer reports conditions that do not meet constraints, allowing you to correct critical timing issues. The following steps describe the basic timing analysis flow: