Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer
ID
683243
Date
10/04/2021
Public
A newer version of this document is available. Customers should click here to go to the newest version.
1.1.1. Timing Path and Clock Analysis
1.1.2. Clock Setup Analysis
1.1.3. Clock Hold Analysis
1.1.4. Recovery and Removal Analysis
1.1.5. Multicycle Path Analysis
1.1.6. Metastability Analysis
1.1.7. Timing Pessimism
1.1.8. Clock-As-Data Analysis
1.1.9. Multicorner Timing Analysis
1.1.10. Time Borrowing
2.1. Timing Analysis Flow
2.2. Step 1: Specify Timing Analyzer Settings
2.3. Step 2: Specify Timing Constraints
2.4. Step 3: Run the Timing Analyzer
2.5. Step 4: Analyze Timing Reports
2.6. Applying Timing Constraints
2.7. Timing Analyzer Tcl Commands
2.8. Timing Analysis of Imported Compilation Results
2.9. Using the Intel® Quartus® Prime Timing Analyzer Document Revision History
2.10. Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer Archive
2.5.1.1. Report Fmax Summary
2.5.1.2. Report Timing
2.5.1.3. Report Data Delay
2.5.1.4. Report Clocks and Clock Networks
2.5.1.5. Report Clock Transfers
2.5.1.6. Report Logic Depth
2.5.1.7. Report Neighbor Paths
2.5.1.8. Report Register Spread
2.5.1.9. Report Route Net of Interest
2.5.1.10. Report Retiming Restrictions
2.5.1.11. Report Reset Statistics
2.5.1.12. Report Pipelining Information
2.5.1.13. Report Asynchronous CDC
2.5.1.14. Report CDC Viewer
2.5.1.15. Report Time Borrowing Data
2.5.1.16. Report Exceptions and Exceptions Reachability
2.6.1. Recommended Initial SDC Constraints
2.6.2. SDC File Precedence
2.6.3. Modifying Iterative Constraints
2.6.4. Using Entity-bound SDC Files
2.6.5. Creating Clocks and Clock Constraints
2.6.6. Creating I/O Constraints
2.6.7. Creating Delay and Skew Constraints
2.6.8. Creating Timing Exceptions
2.6.9. Using Fitter Overconstraints
2.6.10. Example Circuit and SDC File
2.6.8.5.1. Default Multicycle Analysis
2.6.8.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0
2.6.8.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1
2.6.8.5.4. Same Frequency Clocks with Destination Clock Offset
2.6.8.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency
2.6.8.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset
2.6.8.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency
2.6.8.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
2.6.8.4.3. Accounting for a Phase Shift (-phase)
In the following example, the design contains a PLL that performs a phase-shift on a clock whose domain exchanges data with domains that do not experience the phase shift. This occurs when the destination clock phase-shifts forward, and the source clock does not shift. The default setup relationship becomes that phase-shift, thus shifting the window when data is valid.
For example, the following code phase-shifts one output of a PLL forward by a small amount, in this case 0.2 ns.
Cross Domain Phase-Shift
create_generated_clock -source pll|inclk[0] -name pll|clk[0] pll|clk[0]
create_generated_clock -source pll|inclk[0] -name pll|clk[1] -phase 30 pll|clk[1]
The default setup relationship for this phase-shift is 0.2 ns, shown in Figure A, creating a scenario where the hold relationship is negative, which makes achieving timing closure nearly impossible.
Figure 104. Phase-Shifted Setup and Hold
The following constraint allows the data to transfer to the following edge:
set_multicycle_path -setup -from [get_clocks clk_a] -to [get_clocks clk_b] 2
The hold relationship derives from the setup relationship, making a multicycle hold constraint unnecessary.