2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the FIR II IP Core Testbench in MATLAB 2.6. DSP Builder for Intel® FPGAs Design Flow
4.1. FIR II IP Core Interpolation Filters 4.2. FIR Decimation Filters 4.3. FIR II IP Core Time-Division Multiplexing 4.4. FIR II IP Core Multichannel Operation 4.5. FIR II IP Core Multiple Coefficient Banks 4.6. FIR II IP Core Coefficient Reloading 4.7. Reconfigurable FIR Filters 4.8. FIR II IP Core Interfaces and Signals
3.5.1. Memory and Multiplier Trade-Offs
When the Quartus Prime software synthesizes your design to logic, it often creates delay blocks. The FIR II IP core tries to balance the implementation between logic elements (LEs) and memory blocks (M512, M4K, M9K, or M144K). The exact trade-off depends on the target FPGA family, but generally the trade-off attempts to minimize the absolute silicon area used. For example, if a block of RAM occupies the silicon area of two logic array blocks (LABs), a delay requiring more than 20 LEs (two LABs) is implemented as a block of RAM. However, you want to influence this trade-off.
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