FIR II IP Core: User Guide

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ID 683208
Date 8/14/2023
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Document Table of Contents
Document Table of Contents x
1. About the FIR II IP Core 2. FIR II IP Core Getting Started 3. FIR II IP Core Parameters 4. FIR II IP Core Functional Description 5. Document Revision History for the FIR II IP User Guide A. FIR II IP Core Document Archive
1. About the FIR II IP Core x
1.1. DSP Intel® FPGA IP Features 1.2. FIR II IP Core Features 1.3. FIR II IP Device Support 1.4. DSP Intel® FPGA IP Verification 1.5. FIR II IP Core Release Information 1.6. FIR II IP Core Performance and Resource Utilization
2. FIR II IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the FIR II IP Core Testbench in MATLAB 2.6. DSP Builder for Intel® FPGAs Design Flow
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. FIR II IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. FIR II IP Core Parameters x
3.1. FIR II IP Core Filter Specification 3.2. FIR II IP Core Coefficient Settings 3.3. FIR II IP Core Coefficients 3.4. FIR II IP Core Input and Output Options 3.5. FIR II IP Core Implementation Options 3.6. FIR II IP Core Reconfigurability
3.3. FIR II IP Core Coefficients x
3.3.1. Loading Coefficients from a File
3.4. FIR II IP Core Input and Output Options x
3.4.1. Signed Fractional Binary 3.4.2. MSB and LSB Truncation, Saturation, and Rounding
3.5. FIR II IP Core Implementation Options x
3.5.1. Memory and Multiplier Trade-Offs
3.5.1. Memory and Multiplier Trade-Offs x
3.5.1.1. Using Memory Block Threshold 3.5.1.2. Using Dual-port RAM Threshold 3.5.1.3. Using Large RAM Threshold 3.5.1.4. Using Hard Multiplier Threshold
4. FIR II IP Core Functional Description x
4.1. FIR II IP Core Interpolation Filters 4.2. FIR Decimation Filters 4.3. FIR II IP Core Time-Division Multiplexing 4.4. FIR II IP Core Multichannel Operation 4.5. FIR II IP Core Multiple Coefficient Banks 4.6. FIR II IP Core Coefficient Reloading 4.7. Reconfigurable FIR Filters 4.8. FIR II IP Core Interfaces and Signals
4.4. FIR II IP Core Multichannel Operation x
4.4.1. Vectorized Inputs 4.4.2. Channelization 4.4.3. Channel Input and Output Format
4.4.3. Channel Input and Output Format x
4.4.3.1. Eight Channels on Three Wires 4.4.3.2. Four Channels on Four Wires 4.4.3.3. 15 Channels with 15 Valid Cycles and 17 Invalid Cycles 4.4.3.4. 22 Channels with 11 Valid Cycles and 9 Invalid Cycles 4.4.3.5. Super Sample Rate
4.8. FIR II IP Core Interfaces and Signals x
4.8.1. Avalon Streaming Interfaces in DSP Intel FPGA IP 4.8.2. FIR II IP Core Avalon-ST Interfaces 4.8.3. FIR II IP Core Signals
4.8.2. FIR II IP Core Avalon-ST Interfaces x
4.8.2.1. Avalon-ST Sink Interface 4.8.2.2. Avalon-ST Source Interface
4.8.2.1. Avalon-ST Sink Interface x
4.8.2.1.1. Single Channel on Single Wire 4.8.2.1.2. Multiple Channels on Single Wire 4.8.2.1.3. Multiple Channels on Multiple Wires
1. About the FIR II IP Core
2. FIR II IP Core Getting Started
3. FIR II IP Core Parameters
4. FIR II IP Core Functional Description
5. Document Revision History for the FIR II IP User Guide
A. FIR II IP Core Document Archive

4.4.2. Channelization

The number of wires and the number of channels carried on each wire are determined by parameterization, which you can specify using the following variables:
  • clockRate is the system clock frequency (MHz).
  • inputRate is the data sample rate per channel (MSPS).
  • inputChannelNum is the number of channels. Channels are enumerated from 0 to inputChannelNum–1.
  • The period (or TDM factor) is the ratio of the clock rate to the sample rate and determines the number of available time slots.
  • ChanWireCount is the number of channel wires required to carry all the channels. It can be calculated by dividing the number of channels by the TDM factor. More specifically:
    • PhysChanIn = Number of channel input wires
    • PhysChanOut = Number of channel output wires
  • ChanCycleCount is the number of channels carried per wire. It is calculated by dividing the number of channels by the number of channels per wire. The channel signal counts from 0 to ChanCycleCount–1. More specifically:
    • ChansPerPhyIn = Number of channels per input wire
    • ChansPerPhyOut = Number of channels per output wire

If the number of channels is greater than the clock period, multiple wires are required. Each FIR II IP core in your design is internally vectorized to build multiple FIR filters in parallel.

Figure 14. Channelization of Two Channels with a TDM Factor of 3 A TDM factor of 3 combines two input channels into a single output wire. (inputChannelNum = 2, ChanWireCount = 1, ChanCycleCount = 2). This example has three available time slots in the output channel and every third time slot has a ‘don't care’ value when the valid signal is low. The value of the channel signal while the valid signal is low does not matter.
Figure 15. Channelization for Four Channels with a TDM Factor of 3 A TDM factor of 3 combines four input channels into two wires (inputChannelNum = 4, ChanWireCount = 2, ChanCycleCount = 2). This example shows two wires to carry the four channels and the cycle count is two on each wire. The channels are evenly distributed on each wire leaving the third time slot as don't care on each wire.

The channel signal is used for synchronization and scheduling of data. It specifies the channel data separation per wire. Note that the channel signal counts from 0 to ChanCycleCount–1 in synchronization with the data. Thus, for ChanCycleCount = 1, the channel signal is the same as the channel count, enumerated from 0 to inputChannelNum–1.

For a case with single wire, the channel signal is the same as a channel count.

Figure 16. Four Channels on One Wire with No Invalid Cycles

For ChanWireCount > 1, the channel signal specifies the channel data separation per wire, rather than the actual channel number. The channel signal counts from 0 to ChanCycleCount–1 rather than 0 to inputChannelNum–1.

Figure 17. Four Channels on Two Wires with No Invalid Cycles

Notice that the channel signal remains a single wire, not a wire for each data wire. It counts from 0 to ChanCycleCount–1.

Figure 18. Four Channels on Four Wires
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