FIR II IP Core: User Guide

ID 683208
Date 8/14/2023
Document Table of Contents

1.2. FIR II IP Core Features

  • Exploiting maximal designs efficiency through hardware optimizations such as:
    • Interpolation
    • Decimation
    • Symmetry
    • Decimation half-band
    • Time sharing
  • Easy system integration using Avalon® Streaming (Avalon-ST) interfaces.
  • Memory and multiplier trade-offs to balance the implementation between logic elements (LEs) and memory blocks (M512, M4K, M9K, M10K, M20K, or M144K).
  • Support for run-time coefficient reloading capability and multiple coefficient banks.
  • User-selectable output precision via truncation, saturation, and rounding.

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