FIR II IP Core: User Guide

ID 683208
Date 8/14/2023
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4.1. FIR II IP Core Interpolation Filters

An interpolation filter increases the output sample rate by a factor of I through the insertion of I-1 zeros between input samples (zero padding). Polyphase decomposition reduces the number of operations per clock cycle by ignoring the zeros padded in between the original input samples. Polyphase interpolation filters provide both speed and area optimization because each polyphase filter runs at the input data rate for maximum throughput.

Figure 9. Polyphase Interpolation Block Diagram
Figure 10. Polyphase Decomposition for Interpolation Filters

The FIR II IP core implements interpolation filters using a single engine that the different phases timeshare to optimize area. This implementation changes the overall throughput of the filter and the input sample rate. The throughput of the filter is the rate at which the filter generates the output (one output every K clock cycles). The input sample rate is the rate at which the filter processes input data samples (the input needs to be held for L clock cycles).

The values of K and L for the throughput and input sample rate of FIR II interpolation filters depend on the filter architecture.

Table 15.  Definitions of K and L for Different Interpolation Filter Architectures N = input bit width I = interpolation factor, M = number of serial units, C = clocks per output data. The structure of the multibit serial architecture requires the input bit width (N) to be an integer multiple of the number of serial units (M).
Architecture Equations
Fully serial

K = N

L = N I

Multibit serial

K = N/M

L = N I / M

Fully parallel

K = 1

L = I


K = C

L = C I

For systems that require higher throughput and input data rate, Intel recommends that you use parallel or multicycle variable structures.