FIR II IP Core: User Guide

ID 683208
Date 8/14/2023
Document Table of Contents

4.8. FIR II IP Core Interfaces and Signals

The IP core uses an interface controller for the Avalon-ST wrapper that handles the flow control mechanism. The IP core communicates control signals between the sink interface, FIR filter, and source interface via the controller. When designing a datapath that includes the FIR II IP core, you might not need backpressure if you know the downstream components can always receive data. You might achieve a higher clock rate by driving the ast_source_ready signal of the FIR II IP core high, and not connecting the ast_sink_ready signal.

The sink and source interfaces implement the Avalon-ST protocol, which is a unidirectional flow of data. The number of bits per symbol represents the data width and the number of symbols per beat is the number of channel wires. The IP core symbol type supports signed and unsigned binary format. The ready latency on the FIR II IP core is 0.

The clock and reset interfaces drive or receive the clock and reset signals to synchronize the Avalon-ST interfaces and provide reset connectivity.

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