FIR II IP Core: User Guide

ID 683208
Date 8/14/2023
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4.2. FIR Decimation Filters

A decimation filter decreases the output sample rate by a factor of D by keeping only every D-th input sample. Polyphase decomposition reduces the number of computations per cycle by ignoring the input data samples that are discarded during down sampling. Polyphase decimation filters provide speed optimization because each polyphase filter runs at the output data rate.
Figure 11. Decimation Block Diagram
Figure 12. Decimation Polyphase

The FIR II IP core implements decimation filters using a single engine that is time-shared by the different phases to optimize area. This implementation changes the overall throughput of the filter and the input sample rate. The throughput of the filter is the rate at which the filter generates the output (one output every K clock cycles). The input sample rate is the rate at which the filter processes input data samples (the input needs to be held for L clock cycles).

The values of K and L for the throughput and input sample rate of FIR II decimation filters depend on the filter architecture.

Table 16.  Definitions of K and L for Different Decimaiton Filter Architectures N = input bit width D = decimaiton factor, M = number of serial units, C = clocks per output data. The structure of the multibit serial architecture requires the input bit width (N) to be an integer multiple of the number of serial units (M).
Architecture Equations
Fully serial

K = ND

L = N

Multibit serial

K = ND/M

L = N / M

Fully parallel

K = D

L = 1


K = CD

L = C

For systems that require higher throughput and input data rate, Intel recommends that you use parallel or multicycle variable structures.