4.6. FIR II IP Core Coefficient Reloading
Coefficient reloading starts anytime during the filter run time. However, you must reload the coefficients only after you obtain all the desired output data to avoid unpredictable results. If you use multiple coefficient banks, you can reload coefficient banks that are not used and switch over to the new coefficient set when coefficient reloading is complete. You must toggle the coeff_in_areset signal before reloading the coefficient with new data. The new coefficient data is read out after coefficient reloading to verify whether the coefficient reloading process is successful. When the coefficient reloading ends by deasserting the coeff_in_we, the input data is inserted immediately to the filter that is reloaded with the new coefficients.
The symmetrical or anti-symmetrical filters have fewer genuine coefficients, use fewer registers, and require fewer writes to reload the coefficients. For example, only write the first 19 addresses for a 37-tap symmetrical filter. When you write to all 37 addresses, the IP core ignores last 18 addresses because they are not part of the address space of the filter. Similarly, reading coefficient data from the last 18 addresses is also ignored.
When the FIR uses multiple coefficient banks, it arranges the addresses of all the coefficients in consecutive order according to the bank number. The following example shows a 37-tap symmetrical/anti-symmetrical filter with four coefficient banks:
- Address 0–18: Bank 0
- Address 19–37: Bank 1
- Address 38–56: Bank 2
- Address 57–75: Bank 3
The following example shows a 37-tap non-symmetrical/anti-symmetrical filter with 2 coefficient banks:
- Address 0–36: Bank 0
- Address 37–73: Bank 1
If the coefficient bit width parameter is equal to or less than 16 bits, the width of the write data is fixed at 16 bits. If the coefficient bit width parameter is more than 16 bits, the width of the write data is fixed at 32 bits.
The IP core performs a write cycle of 9 clock cycles to reload the whole coefficient data set. To complete the write cycle, assert the coeff_in_we signal, and provide the address (from base address to the max address) together with the new coefficient data. Then, load the new coefficient data into the memory corresponding to the address of the coefficient. The IP core reads new coefficient data during the write cycle when you deassert the coeff_in_we signal. When the coeff_out_valid signal is high, the read data is available on coeff_out_data.
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