FIR II IP Core: User Guide

ID 683208
Date 8/14/2023
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4.3. FIR II IP Core Time-Division Multiplexing

The FIR II IP core optimizes hardware utilization by using time-division multiplexing (TDM). The TDM factor (or folding factor) is the ratio of the clock rate to the sample rate.

By clocking a FIR II IP core faster than the sample rate, you can reuse the same hardware. For example, by implementing a filter with a TDM factor of 2 and an internal clock multiplied by 2, you can halve the required hardware.

Figure 13. Time-Division Multiplexing to Save Hardware Resources

To achieve TDM, the IP core requires a serializer and deserializer before and after the reused hardware block to control the timing. The ratio of system clock frequency to sample rate determines the amount of resource saving except for a small amount of additional logic for the serializer and deserializer.

Table 17.  Estimated Resources Required for a 49-Tap Single Rate Symmetric FIR II IP core Filter
Clock Rate
(MHz) Sample Rate
(MSPS) Logic Multipliers Memory Bits TDM Factor
72 72 2230 25 0 1
144 72 1701 13 468 2
288 72 1145 7 504 4
72 36 1701 13 468 2

When the sample rate equals the clock rate, the filter is symmetric and you only need 25 multipliers. When you increase the clock rate to twice the sample rate, the number of multipliers drops to 13. When the clock rate is set to 4 times the sample rate, the number of multipliers drops to 7. If the clock rate stays the same while the new data sample rate is only 36 MSPS (million samples per second), the resource consumption is the same as twice the sample rate case.