F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 12/17/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

A.2.2.2.3. TPH Requester Control Register (Offset 0x8)

Table 132.  TPH Requester Control Register
Bits Register Description Default Value Access
[2:0 ]
Steering Tag (ST) Mode: This field selects the ST mode:
  • 3'b000 = No Steering Tag Mode
  • 3'b001 = Interrupt Vector Mode
  • 3'b010 = Device-Specific Mode
  • 3'b011 - 3'b111 = Reserved

You need to obtain this information from the configuration intercept interface.

0x0 RW
[7:3] Reserved 0x0 RO
[8]

TPH Requester Enable: When set to 1, the Function is allowed to generate requests with TLP Processing Hints.

You need to obtain this information from the configuration intercept interface.

0x0 RW
[31:9] Reserved 0x0 RO

Did you find the information on this page useful?

Characters remaining:

Feedback Message