F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 12/17/2021
Public

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3.3.3. Avalon-ST TX

The Application Layer transfers data to the Transaction Layer of the PCI Express IP core over the Avalon-ST TX interface. The Transaction Layer must assert tx_st_ready_o before transmission begins. Transmission of a packet must be uninterrupted when tx_st_ready_o is asserted.

This 512-bit interface supports two locations for the beginning of a TLP, bit[0] and bit[256]. The interface supports multiple TLPs per cycle only when an end-of-packet cycle occurs in the lower 256 bits.

This interface supports two tx_st_sop_i signals and two tx_st_eop_i signals per cycle when the F-Tile IP is operating in a x16 configuration. It also does not follow a fixed latency between the tx_st_ready_o and tx_st_valid_i[1:0] signals as specified by the Avalon Interface Specifications. Data can be received any time within the defined readyLatency, which is three coreclkout_hip cycles.

The x16 core provides two segments with each one having 256 bits of data (tx_st_data_i[511:256] and tx_st_data_i[255:0]), 128 bits of header (tx_st_hdr_i[255:128] and tx_st_hdr_i[127:0]), and 32 bits of TLP prefix (tx_st_tlp_prfx_i[63:32] and tx_st_tlp_prfx_i[31:0]). If this core is configured in the 1x16 mode, both segments are used, so the data bus becomes a 512-bit bus tx_st_data_i[511:0]. The start of packet can appear in the upper segment or lower segment, as indicated by the tx_st_sop_i[1:0] signals.

To achieve the expected performance in Gen4 x16 mode, the user application needs to take advantage of this segmented bus architecture. Otherwise, some performance reduction may occur. If this core is configured in the 2x8 mode, only the lower segment is used. In this case, the data bus is a 256-bit bus tx_st_data_i[255:0]. Finally, if this core is configured in the 4x4 mode, only the lower segment is used and only the LSB 128 bits of data are valid. In this case, the data bus is a 128-bit bus tx_st_data_i[127:0]. The x8 core provides one segment with 256 bits of data, 128 bits of header and 32 bits of TLP prefix. If this core is configured in 4x4 mode, only the LSB 128 bits of data are used. The x4 core provides one segment with 128 bits of data, 128 bits of header and 32 bits of TLP prefix.

Figure 20. Avalon-ST TX Packet Interface (x16)
Figure 21. Avalon-ST TX Packet Interface (x8)
Note: The pn prefix is for p0 and p1 for the 2 ports in 2x8 mode.
Figure 22. Avalon-ST TX Packet Interface (x4)
Note: The pn prefix is for p0,p1,p2 and p3 for the 4 ports in 4x4 mode.

The following timing diagram illustrates the behavior of tx_st_ready_o, which is deasserted to pause the data transmission to the Transaction Layer of the F-Tile IP for PCIe, and then reasserted. The timing diagram shows a readyLatency of three cycles. The application deasserts tx_st_valid_i three cycles after tx_st_ready_o is deasserted. The application must not deassert tx_st_valid_i between tx_st_sop_i and tx_st_eop_i on a ready cycle. For the definition of a ready cycle, refer to the Avalon Interface Specifications. This is an additional requirement for the F-Tile IP for PCIe that is not compliant to the Avalon-ST standard.

Figure 23. Avalon-ST TX interface tx_st_ready Behavior

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