F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 12/17/2021
Public

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Document Table of Contents

8.1. Hardware

Typically, PCI Express link-up involves the following steps:
  1. Link training
  2. BIOS enumeration and data transfer

The following sections describe the flow to debug link issues during the hardware bring-up. Intel recommends a systematic approach to diagnosing issues as illustrated in the following figure.

Additionally, you can use the F-Tile Debug Toolkit for debugging the PCIe links when using the F-Tile Avalon-ST IP for PCI Express. The F-Tile Debug Toolkit includes the following features:
  • Protocol and link status information
  • Basic and advanced debugging capabilities including register read access
Figure 71. PCI Express Debug Flow Chart

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