F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 12/17/2021
Public

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3.5. Completion Timeout

The F-Tile IP for PCIe features a Completion timeout mechanism to keep track of Non-Posted requests sent by the user application and the corresponding Completions received. When the F-Tile IP detects a Completion timeout, it notifies the user application by asserting the cpl_timeout_o signal. When a Completion timeout happens, the user application can use the Avalon-MM Interface (for each port) to access the Completion timeout FIFO in the Hard IP to get more detailed information about the event and update the AER capability registers if required. After the completion timeout FIFO becomes empty, the IP core deasserts the cpl_timeout_o signal.

When cpl_timeout_o is asserted, the user application can issue an Avalon-MM Read to retrieve information from the Completion FIFO. Then, it can issue an Avalon-MM Write to write 1 to bit[0] of the CONTROL register to get access to the next data.

Table 18.  Completion Timeout Register
Address Name Access Type Description
0x90000 STATUS RO

[7:2] : Reserved

[1] : Completion timeout FIFO full

[0] : Completion timeout FIFO empty

0x90001 CONTROL WO

[7:1] : Reserved

[0] : Read (popping datafrom the FIFO).

You need to read all the information regarding the timed out request before writing 1 to bit 0 of the CONTROL register.

Writing to bit 0 of the CONTROL register makes the next data appear.

0x90002 VF RO

[7:0] : vfunc_num[7:0]

Virtual Function number for the VF that initiates the nonposted transaction for which the completion timeout is observed.

0x90003 PF RO

[7] : vfunc_active

[6] : Reserved

[5:3] : func_num[2:0] Physical function number (least significant 8 bits) for the PF that initiates the nonposted transaction for which the completion timeout is observed.

[2:0] : vfunc_num[10:8] Virtual Function number (most significant 3 bits) for the VF that initiates the memory read request for which the completion timeout is observed.

0x90004 LEN1 RO

[7:0] : cpl_lenn[7:0] Transfer length in bytes (least significant 8 bits), of the expected completion that timed out for the nonposted transaction.

For a split completion, it indicates the number of bytes remaining to be delivered when the completion timed out (Max length is Max Read request size. Example: 4K Bytes =2^12 bytes)

0x90005 LEN2 RO

[7:4] : Reserved

[3:0] : cpl_lenn[11:8] Transfer length in bytes (most significant 4 bits), of the expected completion that timed out for the nonposted transaction.

For a split completion, it indicates the number of bytes remaining to be delivered when the completion timed out (Max length is Max Read request size. Example: 4K Bytes =2^12 bytes)

0x90006 TAG1 RO

[7:0] : cpl_tag[7:0] Tag ID (least significant 8 bits) of the expected completion that timed out for the non-posted transaction.

0x90007 TAG2 RO

[7:5] : cpl_tc[2:0] Traffic class of the expected completion that timed out for the non-posted transaction.

[4:3] : cpl_attr[1:0] Attribute of the expected completion that timed out for the non-posted transaction. ID based ordering is not supported.
  • [4] -> Relaxed ordering
  • [3]-> No Snoop
  • [2] : Reserved

[1:0]: cpl_tag[9:8] Tag ID (most significant 2 bits) of the expected completion that timed out for the non-posted transaction.

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