3.9. Configuration Intercept Interface (EP Only)
The Configuration Intercept Interface (CII) allows the application logic to detect the occurrence of a Configuration (CFG) request on the link and to modify its behavior. The application logic detects the CFG request at the rising edge of cii_req. Due to the latency of the EMIB, the cii_req can be deasserted many cycles after the deassertion of cii_halt.
- Delay the processing of a CFG request by the controller. This allows the application to perform any housekeeping task first.
- Overwrite the data payload of a CfgWr request. The application logic can also overwrite the data payload of a CfgRd completion TLP.
This interface also allows you to implement the Vendor Specific Extended Capability (VSEC) registers. Example of such implementation is described in following section.
If you are not using this interface, tie cii_halt_i to logic 0.
- Read to last PF's ARI Capability and Control Register.
- All Read/Write access to PF/VF VIRTIO Capability register range.
Implementing Vendor Specific Extended Capability (VSEC) Registers
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