F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 12/17/2021
Public

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3.1.3. Reset

PERST# is defined as Warm Reset that triggers Fundamental Reset by hardware without removal or re-application of power to the device. There is only one PERST# (pin_perst_n) pin on F-Tile. By default, toggling pin_perst_n affects all the PCIE cores in the F-Tile, hence if the F-Tile x16 port is bifurcated into two x8 Endpoints, toggling pin_perst_n affects both x8 Endpoints. To reset each port individually, use the in-band mechanism such as Hot Reset and the Function-Level Reset (FLR).

Following are the guidelines for implementing the F-Tile pin_perst_n reset signal:
  • pin_perst_n is a "power good" indicator from the associated power domain (to which F-Tile is connected). Also, it shall qualify that the reference clocks driving the refclk0 - refclk3 ports are stable. If one of the reference clocks becomes stable later, deassert pin_perst_n after this reference clock becomes stable.
  • pin_perst_n assertion is required for proper Autonomous F-Tile functionality. In Autonomous mode, F-Tile can successfully link up upon the release of pin_perst_n regardless of the FPGA fabric configuration and sends out Configuration Retry Status (CRS) until the FPGA fabric is configured and ready.
  • Avoid performing warm reset or trigger pin_perst_n during a Functional Level Reset or before a Functional Level Reset completion. Warm reset or pin_perst_n is allowed 280 µs upon the de-assertion of p#_flr_rcvd_pf_o across all PFs when Functional Level Reset has been fully acknowledged or completed. Otherwise, the F-Tile PCIe IP configuration may not be reloaded correctly and can cause unexpected behaviour. It is not recoverable until the next warm reset is initiated.
  • The minimum interval requirement between two back-to-back PERST is 50 µs. The minimum interval time required between the deassertion of the PERST to the assertion of the next PERST is 50 µs.

The following is an example where a single PERST# (pin_perst_n) is driven with independent refclk0 and refclk1. In this example, the add-in card (FPGA and SoC) is powered up first. refclk0 input is fed by the on-board free-running oscillator. refclk1 input driven by the Host becomes stable later. Hence, the PERST# is connected to the Host.

Figure 8. Single PERST# Connection in Bifurcated 2x8 Mode

Hot Reset

Hot Reset is supported as per Hot Reset Section decribed in PCIe Base Specification.

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