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1. Acronyms
2. Introduction
3. IP Architecture and Functional Description
4. Advanced Features
5. Interfaces
6. Parameters
7. Testbench
8. Troubleshooting/Debugging
9. F-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide Archives
10. Revision History of the F-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide
A. Configuration Space Registers
B. Implementation of Address Translation Services (ATS) in Endpoint Mode
C. Packets Forwarded to the User Application in TLP Bypass Mode
D. Root Port Enumeration
3.1. Architecture
3.2. Functional Description
3.3. Avalon-ST TX/RX
3.4. Interrupts
3.5. Completion Timeout
3.6. Hot Plug
3.7. Power Management
3.8. Configuration Output Interface (COI)
3.9. Configuration Intercept Interface (EP Only)
3.10. Hard IP Reconfiguration Interface
3.11. PHY Reconfiguration Interface
3.12. Page Request Service (PRS) (EP Only)
5.1. Overview
5.2. Clocks and Resets
5.3. Serial Data Interface
5.4. Avalon-ST Interface
5.5. Interrupt Interface
5.6. Hard IP Status Interface
5.7. Error Interface
5.8. 10-bit Tag Support Interface
5.9. Completion Timeout Interface
5.10. Power Management Interface
5.11. Hot Plug Interface (RP Only)
5.12. Configuration Output Interface
5.13. Configuration Intercept Interface (EP Only)
5.14. Hard IP Reconfiguration Interface
5.15. PHY Reconfiguration Interface
5.16. Page Request Service (PRS) Interface (EP Only)
5.17. FLR Interface Signals
5.18. PTM Interface Signals
5.19. VF Error Flag Interface Signals
5.20. VirtIO PCI Configuration Access Interface Signals
6.2.3.1. Device Capabilities
6.2.3.2. Link Capabilities
6.2.3.3. Legacy Interrupt Pin Register
6.2.3.4. MSI Capabilities
6.2.3.5. MSI-X Capabilities
6.2.3.6. Slot Capabilities
6.2.3.7. Latency Tolerance Reporting (LTR)
6.2.3.8. Process Address Space ID (PASID)
6.2.3.9. Device Serial Number Capability
6.2.3.10. Page Request Service (PRS)
6.2.3.11. Access Control Service (ACS) Capabilities
6.2.3.12. Power Management
6.2.3.13. Vendor Specific Extended Capability (VSEC) Registers
6.2.3.14. Precision Time Measurement (PTM)
6.2.3.15. Address Translation Services (ATS)
6.2.3.16. TLP Processing Hints (TPH)
6.2.3.17. VirtIO Parameters
7.5.1. ebfm_barwr Procedure
7.5.2. ebfm_barwr_imm Procedure
7.5.3. ebfm_barrd_wait Procedure
7.5.4. ebfm_barrd_nowt Procedure
7.5.5. ebfm_cfgwr_imm_wait Procedure
7.5.6. ebfm_cfgwr_imm_nowt Procedure
7.5.7. ebfm_cfgrd_wait Procedure
7.5.8. ebfm_cfgrd_nowt Procedure
7.5.9. BFM Configuration Procedures
7.5.10. BFM Shared Memory Access Procedures
7.5.11. BFM Log and Message Procedures
7.5.12. Verilog HDL Formatting Functions
A.3.1. Intel-Defined VSEC Capability Header (Offset 00h)
A.3.2. Intel-Defined Vendor Specific Header (Offset 04h)
A.3.3. Intel Marker (Offset 08h)
A.3.4. JTAG Silicon ID (Offset 0x0C - 0x18)
A.3.5. User Configurable Device and Board ID (Offset 0x1C - 0x1D)
A.3.6. General Purpose Control and Status Register (Offset 0x30)
A.3.7. Uncorrectable Internal Error Status Register (Offset 0x34)
A.3.8. Uncorrectable Internal Error Mask Register (Offset 0x38)
A.3.9. Correctable Internal Error Status Register (Offset 0x3C)
A.3.10. Correctable Internal Error Mask Register (Offset 0x40)
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4.2.2. Avalon-MM usage for TLP Bypass Mode
The majority of the PCIe standard registers are implemented in the user’s logic outside of the F-Tile Avalon-ST IP. However, the following registers still remain inside the F-Tile:
- Power management capability
- PCI Express capability
- Secondary PCI Express capability
- Data link feature extended capability
- Physical layer 16.0GT/s extended capability
- Lane margining at the receiver extended capability
- Advanced error reporting capability
The application can only access PCIe controller registers through the User Avalon-MM/Hard IP Reconfiguration interface. For more details on the signals in this interface, refer to the Hard IP Reconfiguration Interface.
Capability | Comments |
---|---|
Power Management Capability | Need to write back since it is required to trigger a PCI-PM entry. |
PCI Express Capability | All the PCIe capabilities, control and status registers are for configuring the device. Write-back is required. |
Secondary PCI Express Capability | Secondary PCIe Capability is required for configuring the device. |
Data Link Feature Extended Capability | Data Link Capability is device specific. |
Physical Layer 16.0 GT/s Extended Capability | Physical Layer 16G Capability is device specific. |
Lane Margining at the Receiver Extended Capability | Margining Extended Capability is device specific. |
Advanced Error Reporting Capability | Write-back to error status registers is required for TLP Bypass. |