F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 12/17/2021
Public

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D. Root Port Enumeration

This chapter provides a flow chart that explains the Root Port enumeration process. The goal of enumeration is to find all connected devices in the system and for each connected device, set the necessary registers and make address range assignments.

At the end of the enumeration process, the Root Port (RP) must set the following registers:
  • Primary Bus, Secondary Bus and Subordinate Bus numbers
  • Memory Base and Limit
  • I/O Base and I/O Limit
  • Maximum Payload Size
  • Memory Space Enable bit
The Endpoint (EP) must also have the following registers set by the RP:
  • Master Enable bit
  • BAR Address
  • Maximum Payload Size
  • Memory Space Enable bit
  • Severity bit

The figure below shows an example tree of connected devices on which the following flow chart will be based.

Figure 94. Tree of Connected Devices in Example System
Figure 95. Root Port Enumeration Flow Chart
Figure 96. Root Port Enumeration Flow Chart [Continued]
Figure 97. Root Port Enumeration Flow Chart [Continued]
  1. Vendor ID and Device ID information is located at offset 0x00h for both HeaderType 0 and Header Type 1.
  2. For PCIe Gen4, the Header Type is located at offset 0x0Eh (2nd DW). If bit 0 is setto 1, it indicates the device is a Bridge; otherwise, it is an EP. If bit 7 is set to 0, it indicates this is a single-function device; otherwise, it is a multi-function device.
  3. List of capability registers for RP and non-RP devices: 0x34h – Capabilities Pointers. This register is used to point to a linked list of capabilities implemented by a Function.
    • Capabilities Pointer for RP:
      • Address 60 - Identifies the Power Management Capability ID
      • Address 6c - Identifies MSI Capability ID
      • Address b4 - Identifies the PCI Express Capability structure
    • Capabilities Pointer for non-RP:
      • Address 40 - Identifies Power Management Capability ID
      • Address 48 - Identifies the PCI Express Capability structure
  4. EP does not have an associated register of Primary, Secondary and SubordinateBus numbers.
  5. Bridge/Switch IO Base and Limit register offset 0x1Ch. These registers are set perthe PCIe 4.0 Base Specification. For more accurate information and flow, refer to chapter 7.5.1.3.6 of the Base Specification.
  6. For EP Type 0 header, BAR addresses are located at the following offsets:
    • 0x10h – Base Address 0
    • 0x14h – Base Address 1
    • 0x18h – Base Address 2
    • 0x1ch – Base Address 3
    • 0x20h – Base Address 4
    • 0x24h – Base Address 5
  7. For Bridge/Switch Type 1 header, BAR addresses are located at the following offsets:
    • 0x10h – Base Address 0
    • 0x14h – Base Address 1
  8. For Bridge/Switch Type 1 header, IO Base and IO limit registers are located at offset 0x1Ch.
  9. For Bridge/Switch Type 1 header, Non-Prefetchable Memory Base and Limitregisters are located at offset 0x20h.
  10. For Bridge/Switch Type 1 header, Prefetchable Memory Base and Limit registersare located at offset 0x24h.
  11. For Bridge/Switch/EP Type 0 & 1 headers, the Bus Master Enable bit is located at offset 0x04h (Command Register) bit 2.
  12. For Bridge/Switch/EP Type 0 & 1 headers:
    • I/O Space Enable bit is located at offset 0x04h (Command Register) bit 0.
    • Memory Space Enable bit is located at offset 0x04h (Command Register) bit 1.
    • Bus Master Enable bit is located at offset 0x04h (Command Register) bit 2.
    • Parity Error Response bit is located at offset 0x04h (Command Register) bit 6.
    • SERR# Enable bit is located at offset 0x04h (Command Register) bit 8.
    • Interrupt Disable bit is located at offset 0x04h (Command Register) bit 10.

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