F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 12/17/2021
Public

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6.2.3.13. Vendor Specific Extended Capability (VSEC) Registers

Table 99.  VSEC Register
Parameter Value Default Value Description
Enable CVP (Intel VSEC) True/False False Enables Intel CVP
Vendor Specific Extended Capability True/False False Enables the Vendor Specific Extended Capability (VSEC).
User ID register from the Vendor Specific Extended Capability 0 - 65534 0 Sets the read-only value of the 16-bit User ID register from the Vendor Specific Extended Capability. This parameter is only valid for Endpoints.
Drops Vendor Type0 Messages True/False False

When this parameter is set to 1, the IP core drops vendor Type 0 messages while treating them as Unsupported Requests (UR).

When it is set to 0, the IP core passes these messages on to the user logic.

This option is not applicable for TLP Bypass mode. In TLP Bypass mode, received Vendor MSG Type0 will always be visible on Avalon-ST RX interface.

Drops Vendor Type1 Messages True/False False

When this parameter is set to 1, the IP core silently drops vendor Type 1 messages.

When it is set to 0, the IP core passes these messages on to the user logic.

This option is not applicable for TLP Bypass mode. In TLP Bypass mode, received Vendor MSG Type1 will always be visible on Avalon-ST RX interface.

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