F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 12/17/2021
Public

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8.2.4.1. Main View

The main view tab lists a summary of the transmitter and receiver settings per channel for the given instance of the PCIe IP.

The following table shows the channel mapping when using bifurcated ports.
Table 116.  Channel Mapping for Bifurcated Ports
Toolkit Channel X16 Mode 2X8 Mode
Lane 0 Lane 0 Lane 0
Lane 1 Lane 1 Lane 1
Lane 2 Lane 2 Lane 2
Lane 3 Lane 3 Lane 3
Lane 4 Lane 4 Lane 4
Lane 5 Lane 5 Lane 5
Lane 6 Lane 6 Lane 6
Lane 7 Lane 7 Lane 7
Lane 8 Lane 8 Lane 0
Lane 9 Lane 9 Lane 1
Lane 10 Lane 10 Lane 2
Lane 11 Lane 11 Lane 3
Lane 12 Lane 12 Lane 4
Lane 13 Lane 13 Lane 5
Lane 14 Lane 14 Lane 6
Lane 15 Lane 15 Lane 7

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