F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 12/17/2021
Public

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Document Table of Contents

3.1. Architecture

F-tile PCIe QHIP IP consists of the following major blocks:
  • PMA/PCS (F-Tile General Purpose Transceiver (FGT))
  • Four PCIe cores (one x16 capable core, one x8 capable core and two x4 capable cores). Each core consists of the following layers:
    • Transaction Layer
    • Data Link Layer
  • EMIB
  • Soft Logic blocks
Figure 1. F-Tile Avalon-ST IP for PCI Express Block Diagram

The four cores in the PCIe Hard IP can be configured to support the following topologies

Figure 2. Configuration Modes Supported by the F-tile Avalon-ST IP for PCI Express
Table 8.  Configuration Modes Supported by the F-tile Avalon-ST IP for PCI Express
Topology Description
A

In Topology A, only the x16 Core is active, and it operates as Gen3 x16 core or Gen4 x16 core in Endpoint mode.

B

In Topology B, the x16 Core and x8 Core are active, and they operate as two Gen3 x8 cores or two Gen4 x8 cores in Endpoint mode.

C

In Topology C, all the four cores (x16 Core, x8 Core, x4 Core_0, x4 Core_1) are active, and they operate as four Gen3 x4 cores or four Gen4 x4 cores in Root Port mode.

D

In Topology D, only the x16 Core is active, and it operates as Gen3 x16 core or Gen4 x16 core in Root Port mode.

E

In Topology E, only the x16 Core is active, and it operates as Gen3 x16 core or Gen4 x16 core in Upstream Port mode.

F

In Topology F, the x16 Core and x8 Core are active, and they operate as two Gen3 x8 cores or two Gen4 x8 cores in Upstream Port mode.

G

In Topology G, all the four cores (x16 Core, x8 Core, x4 Core_0, x4 Core_1) are active, and they operate as four Gen3 x4 cores or four Gen4 x4 cores in Upstream Port mode.

H

In Topology H, only the x16 Core is active, and it operates as Gen3 x4 core or Gen4 x4 core in Endpoint mode. Those unused transceiver channels in this topology can be used for Ethernet and other protocols implementation.

I

In Topology I, only the x16 Core is active, and it operates as Gen3 x8 core or Gen4 x8 core in Endpoint mode. Those unused transceiver channels in this topology can be used for Ethernet and other protocols implementation.

J

In Topology J, the x16 Core and x8 Core are active, and they operate as two Gen3 x4 cores or two Gen4 x4 cores in Root Port mode. Those unused transceiver channels in this topology can be used for Ethernet and other protocols implementation.

K

In Topology K, only the x16 Core is active, and it operates as Gen3 x8 core or Gen4 x8 core in Root Port mode. Those unused transceiver channels in this topology can be used for Ethernet and other protocols implementation.

L

In Topology L, only the x16 Core is active, and it operates as Gen3 x16 core or Gen4 x16 core in Downstream Port mode.

M

In Topology M, the x16 Core and x8 Core are active, and they operate as two Gen3 x8 cores or two Gen4 x8 cores in Downstream Port mode.

N

In Topology N, all the four cores (x16 Core, x8 Core, x4 Core_0, x4 Core_1) are active, and they operate as four Gen3 x4 cores or four Gen4 x4 cores in Downstream Port mode.

O

In Topology O, the x16 Core and x8 Core are active, and they operate as two Gen3 x8 cores or two Gen4 x8 cores in Endpoint mode and Upstream Port mode respectively.

P

In Topology P, the x16 Core and x8 Core are active, and they operate as two Gen3 x8 cores or two Gen4 x8 cores in Upstream Port mode and Downstream Port mode respectively.

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