P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 10/07/2021

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Document Table of Contents

2.1.3. Reset

There is only one PERST# (pin_perst_n) pin on P-Tile. Therefore, toggling pin_perst_n will affect the entire P-Tile. If the P-Tile x16 port is bifurcated into two x8 Endpoints, toggling pin_perst_n will affect both x8 Endpoints. To reset each port individually, use the in-band mechanism such as Hot Reset and the Function-Level Reset (FLR). Following are the guidelines for implementing the P-Tile pin_perst_n reset signal:
  • pin_perst_n is a "power good" indicator from the associated power domain (to which P-Tile is connected). Also, it shall qualify that both the P-Tile refclk0 and refclk1 are stable. If one of the reference clocks becomes stable later, deassert pin_perst_n after this reference clock becomes stable.
  • pin_perst_n assertion is required for proper Autonomous P-Tile functionality. In Autonomous mode (enabled by default), P-Tile can successfully link up upon the release of pin_perst_n regardless of the FPGA fabric configuration and will send out CRS (Configuration Retry Status) until the FPGA fabric is configured and ready.
  • Avoid performing a warm reset or triggering pin_perst_n during a functional-level reset or before the functional-level reset completion. Otherwise, the PCIe link may get stuck in reset after the warm reset and cannot recover until cold reset is initiated.

The following is an example where a single PERST# (pin_perst_n) is driven with independent refclk0 and refclk1. In this example, the add-in card (FPGA and Soc) is powered up first. P-Tile refclk0 is fed by the on-board free-running oscillator. P-Tile refclk1 driven by the Host becomes stable later. Hence, the PERST# is connected to the Host.

Figure 5. Single PERST# Connection in Bifurcated 2x8 Mode

P-tile also allows for the implementation of two independent PERST#. For more details, refer to Bifurcated Endpoint Support for Independent Warm Resets .