P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 10/07/2021

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Document Table of Contents Completion Buffer Size

P-tile implements Completion (Cpl) buffers for header and data for each PCIe core. In Endpoint mode, when Completion credits are infinite, user application needs to manage the number of outstanding requests to prevent overflow and lost Completions.

Table 50.  Completion Buffer Size
Completion Buffer Depth Width
Port 0 Cpl header 1144 NA
Port 0 Cpl data 1444 256
Port 1 Cpl header 572 NA
Port 1 Cpl data 1444 128
Port 2 Cpl header 286 NA
Port 2 Cpl data 1444 64
Port 3 Cpl header 286 NA
Port 3 Cpl data 1444 64