P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 10/07/2021

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A.3.9. Correctable Internal Error Status Register (Offset 0x3C)

The Correctable Internal Error Status register reports the status of the internally checked errors that are correctable. When these specific errors are enabled by the Correctable Internal Error Mask register, they are forwarded as correctable internal errors. This register is for debug only. Only use this register to observe behavior, not to drive custom logic

Table 147.  Correctable Internal Error Status Register
Bits Register Description Default Value Access
[31:12] Reserved 0x0 RO
[11] Correctable ECC error status from Config RAM. 0x0 RW1CS
[10:7] Reserved 0x0 RO
[6] Correctable Internal Error reported by the FPGA. 0x0 RW1CS
[5] cvp_config_error_latched: Configuration error detected in CvP mode (to be reported as correctable) - Set whenever cvp_config_error rises while in CvP mode. This bit is only available for Port 0 ( PCIe* Gen4 x16), but not for the other Ports. 0x0 RW1CS
[4:0] Reserved 0x0 RO