P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 10/07/2021

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Document Table of Contents VirtIO PCI Configuration Access BAR Offset Register (Address: 0x039)

This register indicates where the structure begins relative to the base address associated with the BAR. The alignment requirements of the offset are indicated in each structure-specific section.

Table 100.  VirtIO PCI Configuration Access BAR Offset Register
Bit Location Description Access Type Default Value
31:0 BAR Offset RWS Undetermined (*)
Note: (*) Software needs to write the correct value to this register.