P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide
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5.3.4.4. Malformed TLP
In TLP Bypass mode, a malformed TLP is dropped in the P-Tile IP for PCIe and its event is logged in the AER capability registers. P-Tile also notifies you of this event by asserting the serr_out_o signal.
Refer to the PCI Express Base Specification for the definition of a malformed TLP.