P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 10/07/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.6.3. MSI-X

The P-Tile IP for PCIe provides a Configuration Output Interface. User soft logic can monitor this interface to get MSI-X Enable and MSI-X function mask related information. User application logic needs to implement the MSI-X tables for all PFs and VFs at the memory space pointed to by the BARs as a part of your Application Layer.

For more details on the MSI-X related information that you can obtain from the Configuration Output Interface, refer to the MSI-X Registers section in the Registers chapter.

MSI-X is an optional feature that allows the user application to support large amount of vectors with independent message data and address for each vector.

When MSI-X is supported, you need to specify the size and the location (BARs and offsets) of the MSI-X table and PBA. MSI-X can support up to 2048 vectors per function versus 32 vectors per function for MSI.

A function is allowed to send MSI-X messages when MSI-X is enabled and the function is not masked. The application uses the Configuration Output Interface (address 0x0C bit[5:4]) or Configuration Intercept Interface to access this information.

When the application needs to generate an MSI-X, it will use the contents of the MSI-X Table (Address and Data) and generate a Memory Write through the Avalon® -ST interface.

You can enable MSI-X interrupts by turning on the Enable MSI-X option under the PCI Express/PCI Capabilities tab in the parameter editor. If you turn on the Enable MSI-X option, you should implement the MSI-X table structures at the memory space pointed to by the BARs as a part of your Application Layer.

The MSI-X Capability Structure contains information about the MSI-X Table and PBA Structure. For example, it contains pointers to the bases of the MSI-X Table and PBA Structure, expressed as offsets from the addresses in the function's BARs. The Message Control register within the MSI-X Capability Structure also contains the MSI-X Enable bit, the Function Mask bit, and the size of the MSI-X Table. For a picture of the MSI-X Capability Structure, refer to .

MSI-X interrupts are standard Memory Writes, therefore Memory Write ordering rules apply.


Table 55.  MSI-X Configuration
MSI-X Vector MSI-X Upper Address MSI-X Lower Address MSI-X Data
0 0x00000001 0xAAAA0000 0x00000001
1 0x00000001 0xBBBB0000 0x00000002
2 0x00000001 0xCCCC0000 0x00000003
Table 56.  PBA Table
PBA Table PBA Entries
Offset 0 0x0

If the application needs to generate an MSI-X interrupt (vector 1), it will read the MSI-X Table information, generate a MWR TLP through the Avalon® -ST interface and assert the corresponding PBA bits (bit[1]) in a similar fashion as for MSI generation.

The generated TLP will be sent to address 0x00000001_BBBB0000 and the data will be 0x00000002. When the MSI-X has been sent, the application can clear the associated PBA bits.