P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 10/07/2021

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4.4.1. TLP Header and Data Alignment for the Avalon-ST RX and TX Interfaces

The TLP prefix, header and data are sent and received on the TX and RX interfaces.

The ordering of bytes in the header and data portions of packets is different. The first byte of the header dword is located in the most significant byte of the dword. The first byte of the data dword is located in the least significant byte of the dword on the data bus.

Figure 21. Generic TLP Format
Figure 22. TLP Prefix, Header and Data on the RX and TX Interfaces of the P-Tile IP for PCIe