P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide
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Visible to Intel only — GUID: bkc1540407763674
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A.2.2.2.3. TPH Requester Control Register (Offset 0x8)
Bits | Register Description | Default Value | Access |
---|---|---|---|
[2:0 ] |
Steering Tag (ST) Mode: This field selects the ST mode:
You need to obtain this information from the configuration intercept interface. |
0x0 | RW |
[7:3] | Reserved | 0x0 | RO |
[8] | TPH Requester Enable: When set to 1, the Function is allowed to generate requests with TLP Processing Hints. You need to obtain this information from the configuration intercept interface. |
0x0 | RW |
[31:9] | Reserved | 0x0 | RO |