Use of RTL Libraries for FPGA
File or Component
RTL source files
Verilog, System Verilog, or VHDL files that define the RTL component.
Additional files such as Intel® Quartus® Prime IP File (
.qip), Synopsys Design Constraints File (
.sdc), and Tcl Script File (
.tcl) are not allowed.
eXtensible Markup Language File (
Describes the properties of the RTL component. The Intel® oneAPI DPC++/C++ Compiler uses these properties to integrate the RTL component into the SYCL pipeline.
Header file (
A header file containing valid SYCL kernel language and declares the signatures of functions implemented by the RTL component.
Emulation model file (SYCL-based)
Provides a C++ model for the RTL component that is used only for emulation. Full hardware compilations use the RTL source files.
SYCL source files (
Contains definitions of the SYCL functions. These functions are used during emulation and full hardware compilations.
Header file (
A header file describing the functions to be called from SYCL in the SYCL syntax.
- On Linux* platforms, a library is a.aarchive file that contains.oobject files.
- On Windows* platforms, a library is a.libarchive file that contains.objobject files.
- Each object file is created from an input source file using thefpga_crossgencommand.
- An object file is effectively an intermediate representation of your source code with both a CPU representation and an FPGA representation of your code.
- An object can be targeted for use with only one Intel® high-level design product. If you want to target more than one high-level design product, you must generate a separate object for each target product.
- Object files are combined into a library file using thefpga_libtoolcommand. Objects created from different types of source code can be combined into a library, provided all objects target the same high-level design product.A library is automatically assigned a toolchain version number and can be used only with the targeted high-level design product with the same version number.
Create Library Objects From Source Code
Create an Object File From Source Code
fpga_crossgen <rtl_spec>.xml --emulation_model <emulation_model>.cpp --target sycl -o <object_file>
An XML file name that specifies the details about your RTL library.
Targets an Intel® high-level design tool (
sycl) for the library. The objects are combined as object files into a SYCL library archive file using the
Optional flag. This option helps you specify an object file name. If you do not specify this option, the object file name defaults to be the same name as the source code file name but with an object file suffix (
fpga_crossgen lib_rtl_spec.xml --emulation_model lib_rtl_model.cpp --source sycl --target sycl -o lib_rtl.o
Packaging Object Files into a Library File
fpga_libtool file1 file2 ... fileN --target (sycl) --create <library_name>
file1 file2 ... fileN
You can specify one or more object files to include in the library.
Target this library for kernels developed. When you mention the
--targetprepares the library for use with the Intel® oneAPI DPC++/C++ Compiler.
Allows you to specify the name of the library archive file. Specify the file extension of the library file as
.afor Linux-platform libraries.
fpga_libtool lib_rtl.o --target sycl --create lib.a
Using Static Libraries
dpcpp -fintelfpga main.cpp lib.a
SYCL_EXTERNAL extern "C" void foo()