FPGA Compilation Flags
# FPGA emulator image dpcpp -fintelfpga -DFPGA_EMULATOR fpga_compile.cpp -o fpga_compile.fpga_emu # FPGA simulator image dpcpp -fintelfpga fpga_compile.cpp -Xssimulation -Xsboard=intel_s10sx_pac:pac_s10 # FPGA early image (with optimization report): default board dpcpp -fintelfpga -Xshardware -fsycl-link=early fpga_compile.cpp -o fpga_compile_report.a # FPGA early image (with optimization report): explicit board dpcpp -fintelfpga -Xshardware -fsycl-link=early -Xsboard=intel_s10sx_pac:pac_s10 fpga_compile.cpp -o fpga_compile_report.a # FPGA hardware image: default board dpcpp -fintelfpga -Xshardware fpga_compile.cpp -o fpga_compile.fpga # FPGA hardware image: explicit board dpcpp -fintelfpga -Xshardware -Xsboard=intel_s10sx_pac:pac_s10 fpga_compile.cpp -o fpga_compile.fpga
Performs ahead-of-time (offline) compilation for FPGA.
Adds a preprocessor define (see code snippet above).
Instructs the compiler to target FPGA hardware. If you omit this flag, the compiler targets the default FPGA target, which is FPGA emulator.
Using the prefix
-Xscauses an argument to be passed to the FPGA backend.
Instructs the compiler to stop after creating the FPGA early image (and associated optimization report).
[Optional argument] Specifies the FPGA board variant and BSP. If omitted, the compiler chooses the default FPGA board variant
intel_a10gx_pac BSP. Refer to the FPGA BSPs and Boards section for additional details.
Other SYCL FPGA Flags Supported by the Compiler
Prints out FPGA-specific options for the
Instructs the compiler to extract the compiled FPGA hardware image from the existing executable and package it into the new executable, saving the device compilation time. This option is useful only when compiling for hardware. Refer to the Fast Recompile for FPGA section for additional information.
FPGA backend generates a verbose output describing the progress of the compilation.
Generates an emulator device image. This is the default behavior.
Generates a simulator device image.
Causes the simulation flow to log signals to Siemens EDA
(formerly Mentor Graphics)Questa* waveform files.
Use the optional
<depth>attribute to specify how many levels of hierarchy are logged. If you do not specify a value for the
<depth>attribute, all signals are logged.
Sets the degree of parallelism used in the FPGA bitstream compilation.
<num_threads>value specifies the number of parallel threads you want to use. The maximum recommended value is the number of available cores. Setting this flag is optional. The default behavior is for the Intel® Quartus® Prime software to compile in parallel on all available cores.
Sets the seed used by Intel® Quartus® Prime software when generating the FPGA bitstream. The value must be an unsigned integer, and by default the value is 1.
Runs FPGA bitstream compilation with reduced effort. This option allows faster compile time but at a cost of reduced performance of the compiled FPGA hardware image. Use this flag only for faster development time. It is not intended for production quality results.