Programming Guide


FPGA Compilation Flags

FPGA compilation flags control the FPGA image type the Intel® oneAPI DPC++/C++ Compiler targets.
The following are examples of Intel® oneAPI DPC++/C++ Compiler commands that target the FPGA image types:
// FPGA emulator image dpcpp -fintelfpga fpga_compile.cpp -o fpga_compile.fpga_emu // FPGA simulator image dpcpp -fintelfpga fpga_compile.cpp -Xssimulation -Xsboard=intel_s10sx_pac:pac_s10 // FPGA early image (with optimization report): default board dpcpp -fintelfpga -Xshardware -fsycl-link=early fpga_compile.cpp -o fpga_compile_report.a // FPGA early image (with optimization report): explicit board dpcpp -fintelfpga -Xshardware -fsycl-link=early -Xsboard=intel_s10sx_pac:pac_s10 fpga_compile.cpp -o fpga_compile_report.a // FPGA hardware image: default board dpcpp -fintelfpga -Xshardware fpga_compile.cpp -o fpga_compile.fpga // FPGA hardware image: explicit board dpcpp -fintelfpga -Xshardware -Xsboard=intel_s10sx_pac:pac_s10 fpga_compile.cpp -o fpga_compile.fpga
The following table explains the compiler flags used in the above example commands:
FPGA Compilation Flags
Performs ahead-of-time (offline) compilation for FPGA.
Instructs the compiler to target FPGA hardware. If you omit this flag, the compiler targets the default FPGA target, which is the FPGA emulator.
Using the prefix
causes an argument to be passed to the FPGA backend.
Instructs the compiler to stop after creating the FPGA early image (and associated optimization report).
[Optional argument] Specifies the FPGA board variant and BSP. If omitted, the compiler chooses the default FPGA board variant
from the
intel_a10gx_pac BSP
. Refer to the FPGA BSPs and Boards section for additional details.
The output of a
compile command overwrites the output of previous compiles that used the same output name. Therefore, Intel® recommends using unique output names (specified with
). This is especially important for FPGA compilation since a lost hardware image may take hours to regenerate.
In addition to the compiler flags demonstrated by the commands above, there are flags to control the verbosity of the
command’s output, the number of parallel threads to use during compilation, and so on. The following section briefly describes those flags.

Other SYCL* FPGA Flags Supported by the Compiler

The Intel® oneAPI DPC++/C++ Compiler offers several options that allow you to customize the kernel compilation process. The following table summarizes other options supported by the compiler:
Other Supported FPGA Flags
Option name
Prints out FPGA-specific options for the
  • -fsycl-link=early
    is synonymous with
    . Both instruct the compiler to stop after creating the FPGA early image (and the associated optimization report).
  • -fsycl-link=image
    is used in the device link compilation flow to instruct the compiler to generate the FPGA hardware image. Refer to the Fast Recompile for FPGA section for additional information.
Instructs the compiler to extract the compiled FPGA hardware image from the existing executable and package it into the new executable, saving the device compilation time. This option is applicable only when compiling for hardware. Refer to the Fast Recompile for FPGA section for additional information.
FPGA backend generates a verbose output describing the progress of the compilation.
Generates an emulator device image. This is the default behavior.
Generates a simulator device image.
Causes the simulation flow to log signals to Siemens EDA
(formerly Mentor Graphics)
Questa* waveform files.
Use the optional
attribute to specify how many levels of hierarchy are logged. If you do not specify a value for the
attribute, all signals are logged.
Sets the degree of parallelism used in the FPGA bitstream compilation.
value specifies the number of parallel threads you want to use. The maximum recommended value is the number of available cores. Setting this flag is optional. The default behavior is for the Intel® Quartus® Prime software to compile in parallel on all available cores.
Sets the seed used by Intel® Quartus® Prime software when generating the FPGA bitstream. The value must be an unsigned integer, and by default, the value is 1.
Runs FPGA bitstream compilation with reduced effort. This option allows faster compile time but at the cost of reduced performance of the compiled FPGA hardware image. Use this flag only for faster development time. It is not intended for production-quality results.
flag is equivalent to setting the QSF setting
. This QSF setting mainly sets the Intel Quartus Prime software into the compile mode that is dominated by the Fast Functional Test.
For more information about FPGA optimization flags, refer to the Optimization Flags section in the
FPGA Optimization Guide for Intel® oneAPI Toolkits

Product and Performance Information


Performance varies by use, configuration and other factors. Learn more at